re PR target/66369 (gcc 4.8.3/5.1.0 miss optimisation with vpmovmskb)

	PR target/66369
	* config/i386/sse.md (<sse2_avx2>_pmovmsk): Merge from avx2_pmovmskb
	and sse2_pmovmskb using VI1_AVX2 mode iterator.
	(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): New insn pattern.
	(*<sse2_avx2>_pmovmskb_zext): Ditto.

From-SVN: r224120

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 53d75b1c69f6e8ffecc76b02862e446f0916fdf6..78d46132672ddb8c4ad37801dbf62d4ed6c93733 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1125,7 +1125,7 @@
        ACX_PROG_CXX_WARNING_ALMOST_PEDANTIC, and
        ACX_PROG_CXX_WARNINGS_ARE_ERRORS.
 
-2015-05-22 Aditya Kumar <hiraditya@msn.com>
+2015-05-22  Aditya Kumar  <hiraditya@msn.com>
 
        * auto-profile.c (afdo_calculate_branch_prob): Break once has_sample
        is true.
@@ -3398,7 +3398,7 @@
        (aarch_macro_fusion_pair_p): Update uses of current_tune.
        * arm.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Likewise.
 
-2015-05-12 Sandra Loosemore <sandra@codesourcery.com>
+2015-05-12  Sandra Loosemore  <sandra@codesourcery.com>
 
        * config/nios2/nios2.md (trap, ctrapsi4): Use "trap" instead of
        "break".

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 21c6c6cd5be6c6f8fd5daee4af919146bf660e4f..e44ba9a6d366444bc598642530f33d69f9bbfe17 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -13112,24 +13112,48 @@
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "avx2_pmovmskb"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-       (unspec:SI [(match_operand:V32QI 1 "register_operand" "x")]
-                  UNSPEC_MOVMSK))]
-  "TARGET_AVX2"
-  "vpmovmskb\t{%1, %0|%0, %1}"
+(define_insn "*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (unspec:SI
+           [(match_operand:VF_128_256 1 "register_operand" "x")]
+           UNSPEC_MOVMSK)))]
+  "TARGET_64BIT && TARGET_SSE"
+  "%vmovmsk<ssemodesuffix>\t{%1, %k0|%k0, %1}"
   [(set_attr "type" "ssemov")
-   (set_attr "prefix" "vex")
-   (set_attr "mode" "DI")])
+   (set_attr "prefix" "maybe_vex")
+   (set_attr "mode" "<MODE>")])
 
-(define_insn "sse2_pmovmskb"
+(define_insn "<sse2_avx2>_pmovmskb"
   [(set (match_operand:SI 0 "register_operand" "=r")
-       (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
-                  UNSPEC_MOVMSK))]
+       (unspec:SI
+         [(match_operand:VI1_AVX2 1 "register_operand" "x")]
+         UNSPEC_MOVMSK))]
   "TARGET_SSE2"
   "%vpmovmskb\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
-   (set_attr "prefix_data16" "1")
+   (set (attr "prefix_data16")
+     (if_then_else
+       (match_test "TARGET_AVX")
+     (const_string "*")
+     (const_string "1")))
+   (set_attr "prefix" "maybe_vex")
+   (set_attr "mode" "SI")])
+
+(define_insn "*<sse2_avx2>_pmovmskb_zext"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+       (zero_extend:DI
+         (unspec:SI
+           [(match_operand:VI1_AVX2 1 "register_operand" "x")]
+           UNSPEC_MOVMSK)))]
+  "TARGET_64BIT && TARGET_SSE2"
+  "%vpmovmskb\t{%1, %k0|%k0, %1}"
+  [(set_attr "type" "ssemov")
+   (set (attr "prefix_data16")
+     (if_then_else
+       (match_test "TARGET_AVX")
+     (const_string "*")
+     (const_string "1")))
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "SI")])