assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
info->has_graphics = gfx.available_rings > 0;
- info->num_rings[RING_DMA] = util_bitcount(dma.available_rings);
+ info->num_rings[RING_GFX] = util_bitcount(gfx.available_rings);
info->num_rings[RING_COMPUTE] = util_bitcount(compute.available_rings);
+ info->num_rings[RING_DMA] = util_bitcount(dma.available_rings);
+ info->num_rings[RING_UVD] = util_bitcount(uvd.available_rings);
+ info->num_rings[RING_VCE] = util_bitcount(vce.available_rings);
+ info->num_rings[RING_UVD_ENC] = util_bitcount(uvd_enc.available_rings);
+ info->num_rings[RING_VCN_DEC] = util_bitcount(vcn_dec.available_rings);
+ info->num_rings[RING_VCN_ENC] = util_bitcount(vcn_enc.available_rings);
+ info->num_rings[RING_VCN_JPEG] = util_bitcount(vcn_jpeg.available_rings);
/* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
* on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
printf("Features:\n");
printf(" has_graphics = %i\n", info->has_graphics);
- printf(" num_rings[RING_COMPUTE] = %u\n", info->num_rings[RING_COMPUTE]);
+ printf(" num_rings[RING_GFX] = %i\n", info->num_rings[RING_GFX]);
printf(" num_rings[RING_DMA] = %i\n", info->num_rings[RING_DMA]);
+ printf(" num_rings[RING_COMPUTE] = %u\n", info->num_rings[RING_COMPUTE]);
+ printf(" num_rings[RING_UVD] = %i\n", info->num_rings[RING_UVD]);
+ printf(" num_rings[RING_VCE] = %i\n", info->num_rings[RING_VCE]);
+ printf(" num_rings[RING_UVD_ENC] = %i\n", info->num_rings[RING_UVD_ENC]);
+ printf(" num_rings[RING_VCN_DEC] = %i\n", info->num_rings[RING_VCN_DEC]);
+ printf(" num_rings[RING_VCN_ENC] = %i\n", info->num_rings[RING_VCN_ENC]);
+ printf(" num_rings[RING_VCN_JPEG] = %i\n", info->num_rings[RING_VCN_JPEG]);
printf(" has_clear_state = %u\n", info->has_clear_state);
printf(" has_distributed_tess = %u\n", info->has_distributed_tess);
printf(" has_dcc_constant_encode = %u\n", info->has_dcc_constant_encode);
ws->info.has_dedicated_vram = true;
}
+ ws->info.num_rings[RING_GFX] = 1;
/* Check for dma */
ws->info.num_rings[RING_DMA] = 0;
/* DMA is disabled on R700. There is IB corruption and hangs. */
if (ws->info.drm_minor >= 32) {
uint32_t value = RADEON_CS_RING_UVD;
if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
- "UVD Ring working", &value))
+ "UVD Ring working", &value)) {
ws->info.has_hw_decode = value;
+ ws->info.num_rings[RING_UVD] = 1;
+ }
value = RADEON_CS_RING_VCE;
if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
NULL, &value) && value) {
if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
- "VCE FW version", &value))
+ "VCE FW version", &value)) {
ws->info.vce_fw_version = value;
+ ws->info.num_rings[RING_VCE] = 1;
+ }
}
}