inorder: don't stall after stores

once a ST is sent off, it's OK to keep processing, however it's a little more
complicated to handle the packet acknowledging the store is completed

diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 83eb617aa9a5a7505e95301f542ef0ad214837cf..c627466a18700a57d69c3b93373b147b1ce32aa0 100644 (file)
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -240,17 +240,17 @@ CacheUnit::removeAddrDependency(DynInstPtr inst)
     inst->unsetMemAddr();
 
     // Erase from Address List
-    vector<Addr>::iterator vect_it = find(addrList[tid].begin(),
+    std::list<Addr>::iterator list_it = find(addrList[tid].begin(),
                                           addrList[tid].end(),
                                           mem_addr);
-    assert(vect_it != addrList[tid].end() || inst->splitInst);
+    assert(list_it != addrList[tid].end() || inst->splitInst);
 
-    if (vect_it != addrList[tid].end()) {
+    if (list_it != addrList[tid].end()) {
         DPRINTF(AddrDep,
                 "[tid:%i]: [sn:%i] Address %08p removed from dependency "
-                "list\n", inst->readTid(), inst->seqNum, (*vect_it));
+                "list\n", inst->readTid(), inst->seqNum, (*list_it));
 
-        addrList[tid].erase(vect_it);
+        addrList[tid].erase(list_it);
 
         // Erase From Address Map (Used for Debugging)
         addrMap[tid].erase(addrMap[tid].find(mem_addr));

diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh
index 7daf5f4a0a12f9ff593b881d469cffe805688a99..dd6fa763878173a4b757d593675ca8bc9e95ada6 100644 (file)
--- a/src/cpu/inorder/resources/cache_unit.hh
+++ b/src/cpu/inorder/resources/cache_unit.hh
@@ -187,9 +187,9 @@ class CacheUnit : public Resource
 
     bool cachePortBlocked;
 
-    std::vector<Addr> addrList[ThePipeline::MaxThreads];
+    std::list<Addr> addrList[ThePipeline::MaxThreads];
 
-    std::map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
+    m5::hash_map<Addr, InstSeqNum> addrMap[ThePipeline::MaxThreads];
 
   public:
     int cacheBlkSize;