[sim,xcc] Changed instruction format to RISC-V

Massive changes to gcc, binutils to support new instruction encoding.
Simulator reflects these changes.

diff --git a/riscv/applink.cc b/riscv/applink.cc
index 0937067dfeec48b8935da83898283dbbc5ecd3d3..d8fddaded421420c9e11b67be094d16b86a4a5e7 100644 (file)
--- a/riscv/applink.cc
+++ b/riscv/applink.cc
@@ -80,7 +80,7 @@ int appserver_link_t::wait_for_packet()
   {
     packet p;
     int bytes = read(fromhost_fd,&p,sizeof(p));
-    if(bytes < offsetof(packet,data))
+    if(bytes < (signed)offsetof(packet,data))
       throw io_error("read failed");
   
     if(p.seqno != seqno)

diff --git a/riscv/common.h b/riscv/common.h
index 447d6311226380d4e63e667de2a4c2e7828d16eb..cbb8e958cabae496b61ac916f1ec2d124cd796ae 100644 (file)
--- a/riscv/common.h
+++ b/riscv/common.h
@@ -20,4 +20,6 @@
       print_and_die(__str); \
     } } while(0)
 
+#define static_assert(x)       switch (x) case 0: case (x):
+
 #endif

diff --git a/riscv/decode.h b/riscv/decode.h
index ded38abbc69eced2c9efeb300b6a59728848da0f..40c79f72ca23cc75cb371a6391d44520a18f08e1 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -2,12 +2,15 @@
 #define _RISCV_DECODE_H
 
 #include <stdint.h>
+typedef int int128_t __attribute__((mode(TI)));
+typedef unsigned int uint128_t __attribute__((mode(TI)));
 
 #define support_64bit 1
 typedef int64_t sreg_t;
 typedef uint64_t reg_t;
 
-const int OPCODE_BITS = 6;
+const int OPCODE_BITS = 7;
+const int JTYPE_OPCODE_BITS = 5;
 
 const int GPR_BITS = 8*sizeof(reg_t);
 const int GPRID_BITS = 5;
@@ -17,10 +20,11 @@ const int FPR_BITS = 64;
 const int FPRID_BITS = 5;
 const int NFPR = 1 << FPRID_BITS;
 
-const int IMM_BITS = 16;
-const int TARGET_BITS = 26;
-const int SHAMT_BITS = 5;
-const int FUNCT_BITS = 6;
+const int IMM_BITS = 12;
+const int TARGET_BITS = 27;
+const int SHAMT_BITS = 6;
+const int FUNCT_BITS = 3;
+const int BIGIMM_BITS = 20;
 
 #define SR_ET    0x0000000000000001ULL
 #define SR_PS    0x0000000000000004ULL
@@ -35,24 +39,33 @@ const int FUNCT_BITS = 6;
 struct itype_t
 {
   unsigned imm : IMM_BITS;
-  unsigned rt : GPRID_BITS;
-  unsigned rs : GPRID_BITS;
+  unsigned funct : FUNCT_BITS;
+  unsigned rb : GPRID_BITS;
+  unsigned ra : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
 struct jtype_t
 {
   unsigned target : TARGET_BITS;
-  unsigned opcode : OPCODE_BITS;
+  unsigned jump_opcode : JTYPE_OPCODE_BITS;
 };
 
 struct rtype_t
 {
-  unsigned funct : FUNCT_BITS;
+  unsigned rc : GPRID_BITS;
   unsigned shamt : SHAMT_BITS;
-  unsigned rd : GPRID_BITS;
+  unsigned unused : 1;
+  unsigned funct : FUNCT_BITS;
+  unsigned rb : GPRID_BITS;
+  unsigned ra : GPRID_BITS;
+  unsigned opcode : OPCODE_BITS;
+};
+
+struct btype_t
+{
+  unsigned bigimm : BIGIMM_BITS;
   unsigned rt : GPRID_BITS;
-  unsigned rs : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
@@ -61,19 +74,21 @@ union insn_t
   itype_t itype;
   jtype_t jtype;
   rtype_t rtype;
+  btype_t btype;
   uint32_t bits;
 };
 
 // helpful macros, etc
-#define RS R[insn.rtype.rs]
-#define RT R[insn.rtype.rt]
-#define RD R[insn.rtype.rd]
+#define RA R[insn.rtype.ra]
+#define RB R[insn.rtype.rb]
+#define RC R[insn.rtype.rc]
+#define BIGIMM insn.btype.bigimm
 #define IMM insn.itype.imm
-#define SIMM ((int16_t)insn.itype.imm)
+#define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS))
 #define SHAMT insn.rtype.shamt
 #define TARGET insn.jtype.target
 #define BRANCH_TARGET (npc + (SIMM*sizeof(insn_t)))
-#define JUMP_TARGET ((npc & ~((1<<TARGET_BITS)-1)) + TARGET*sizeof(insn_t))
+#define JUMP_TARGET ((npc & ~((1<<TARGET_BITS)*sizeof(insn_t)-1)) + TARGET*sizeof(insn_t))
 
 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 #define require64 if(gprlen != 64) throw trap_illegal_instruction

diff --git a/riscv/execute.h b/riscv/execute.h
index 66ce0e061b5691e2b8a1dd4e70f4f2a454fd6603..54bf52d294e7544771f312dee2a045a39d21ba77 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -1,635 +1,1147 @@
 /* Automatically generated by parse-opcodes */
-switch(opcode)
+switch((insn.bits >> 0x19) & 0x7f)
 {
-  case 0:
+  case 0x0:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      switch(funct)
-      {
-        case 0:
-          {
-            #include "insns/unimp.h"
-          }
-          break;
-        case 1:
-          {
-            #include "insns/sll.h"
-          }
-          break;
-        case 2:
-          {
-            #include "insns/srl.h"
-          }
-          break;
-        case 3:
-          {
-            #include "insns/sra.h"
-          }
-          break;
-        case 5:
-          {
-            #include "insns/sllv.h"
-          }
-          break;
-        case 6:
-          {
-            #include "insns/srlv.h"
-          }
-          break;
-        case 7:
-          {
-            #include "insns/srav.h"
-          }
-          break;
-        case 9:
-          {
-            #include "insns/jalr.h"
-          }
-          break;
-        case 10:
-          {
-            #include "insns/movz.h"
-          }
-          break;
-        case 11:
-          {
-            #include "insns/movn.h"
-          }
-          break;
-        case 12:
-          {
-            #include "insns/syscall.h"
-          }
-          break;
-        case 13:
-          {
-            #include "insns/break.h"
-          }
-          break;
-        case 14:
-          {
-            #include "insns/rdhwr.h"
-          }
-          break;
-        case 15:
-          {
-            #include "insns/sync.h"
-          }
-          break;
-        case 17:
-          {
-            #include "insns/dsll.h"
-          }
-          break;
-        case 18:
-          {
-            #include "insns/dsrl.h"
-          }
-          break;
-        case 19:
-          {
-            #include "insns/dsra.h"
-          }
-          break;
-        case 21:
-          {
-            #include "insns/dsllv.h"
-          }
-          break;
-        case 22:
-          {
-            #include "insns/dsrlv.h"
-          }
-          break;
-        case 23:
-          {
-            #include "insns/dsrav.h"
-          }
-          break;
-        case 25:
-          {
-            #include "insns/dsll32.h"
-          }
-          break;
-        case 26:
-          {
-            #include "insns/dsrl32.h"
-          }
-          break;
-        case 27:
-          {
-            #include "insns/dsra32.h"
-          }
-          break;
-        case 32:
-          {
-            #include "insns/add.h"
-          }
-          break;
-        case 33:
-          {
-            #include "insns/sub.h"
-          }
-          break;
-        case 34:
-          {
-            #include "insns/slt.h"
-          }
-          break;
-        case 35:
-          {
-            #include "insns/sltu.h"
-          }
-          break;
-        case 36:
-          {
-            #include "insns/and.h"
-          }
-          break;
-        case 37:
-          {
-            #include "insns/or.h"
-          }
-          break;
-        case 38:
-          {
-            #include "insns/xor.h"
-          }
-          break;
-        case 39:
-          {
-            #include "insns/nor.h"
-          }
-          break;
-        case 40:
-          {
-            #include "insns/mul.h"
-          }
-          break;
-        case 48:
-          {
-            #include "insns/dadd.h"
-          }
-          break;
-        case 49:
-          {
-            #include "insns/dsub.h"
-          }
-          break;
-        case 56:
-          {
-            #include "insns/dmul.h"
-          }
-          break;
-        default:
-          {
-            #include "insns/unimp.h"
-          }
+      case 0x0:
+      {
+        if((insn.bits & 0xffffffff) == 0x0)
+        {
+          #include "insns/unimp.h"
           break;
         }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 1:
-    {
-      #include "insns/synci.h"
-    }
-    break;
-  case 2:
-    {
-      #include "insns/j.h"
-    }
-    break;
-  case 3:
-    {
-      #include "insns/jal.h"
-    }
-    break;
-  case 4:
-    {
-      #include "insns/beq.h"
-    }
-    break;
-  case 5:
-    {
-      #include "insns/bne.h"
-    }
+  }
+  case 0x60:
+  {
+    #include "insns/j.h"
     break;
-  case 8:
-    {
-      #include "insns/addi.h"
-    }
+  }
+  case 0x61:
+  {
+    #include "insns/j.h"
     break;
-  case 10:
-    {
-      #include "insns/slti.h"
-    }
+  }
+  case 0x62:
+  {
+    #include "insns/j.h"
     break;
-  case 11:
-    {
-      #include "insns/sltiu.h"
-    }
+  }
+  case 0x63:
+  {
+    #include "insns/j.h"
     break;
-  case 12:
-    {
-      #include "insns/andi.h"
-    }
+  }
+  case 0x64:
+  {
+    #include "insns/jal.h"
     break;
-  case 13:
-    {
-      #include "insns/ori.h"
-    }
+  }
+  case 0x65:
+  {
+    #include "insns/jal.h"
     break;
-  case 14:
-    {
-      #include "insns/xori.h"
-    }
+  }
+  case 0x66:
+  {
+    #include "insns/jal.h"
     break;
-  case 15:
-    {
-      #include "insns/lui.h"
-    }
+  }
+  case 0x67:
+  {
+    #include "insns/jal.h"
     break;
-  case 16:
+  }
+  case 0x68:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      switch(funct)
+      case 0x0:
       {
-        case 0:
-          {
-            #include "insns/ei.h"
-          }
+        if((insn.bits & 0xfe007c00) == 0xd0000000)
+        {
+          #include "insns/add_fmt.h"
           break;
-        case 1:
-          {
-            #include "insns/di.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd0001000)
+        {
+          #include "insns/sub_fmt.h"
           break;
-        case 2:
-          {
-            #include "insns/eret.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd0002000)
+        {
+          #include "insns/mul_fmt.h"
           break;
-        case 24:
-          {
-            #include "insns/mfc0.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd0003000)
+        {
+          #include "insns/div_fmt.h"
           break;
-        case 25:
-          {
-            #include "insns/dmfc0.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd0004000)
+        {
+          #include "insns/sqrt_fmt.h"
           break;
-        case 28:
-          {
-            #include "insns/mtc0.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd0005000)
+        {
+          #include "insns/abs_fmt.h"
           break;
-        case 29:
-          {
-            #include "insns/dmtc0.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd0006000)
+        {
+          #include "insns/mov_fmt.h"
           break;
-        default:
-          {
-            #include "insns/unimp.h"
-          }
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd0007000)
+        {
+          #include "insns/neg_fmt.h"
           break;
         }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 17:
+  }
+  case 0x69:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      switch(funct)
-      {
-        case 0:
-          {
-            #include "insns/add_fmt.h"
-          }
-          break;
-        case 1:
-          {
-            #include "insns/sub_fmt.h"
-          }
-          break;
-        case 2:
-          {
-            #include "insns/mul_fmt.h"
-          }
-          break;
-        case 3:
-          {
-            #include "insns/div_fmt.h"
-          }
-          break;
-        case 4:
-          {
-            #include "insns/sqrt_fmt.h"
-          }
-          break;
-        case 5:
-          {
-            #include "insns/abs_fmt.h"
-          }
-          break;
-        case 6:
-          {
-            #include "insns/mov_fmt.h"
-          }
-          break;
-        case 7:
-          {
-            #include "insns/neg_fmt.h"
-          }
-          break;
-        case 8:
-          {
-            #include "insns/round_l_fmt.h"
-          }
-          break;
-        case 9:
-          {
-            #include "insns/trunc_l_fmt.h"
-          }
-          break;
-        case 10:
-          {
-            #include "insns/ceil_l_fmt.h"
-          }
-          break;
-        case 11:
-          {
-            #include "insns/floor_l_fmt.h"
-          }
-          break;
-        case 12:
-          {
-            #include "insns/round_w_fmt.h"
-          }
-          break;
-        case 13:
-          {
-            #include "insns/trunc_w_fmt.h"
-          }
-          break;
-        case 14:
-          {
-            #include "insns/ceil_w_fmt.h"
-          }
-          break;
-        case 15:
-          {
-            #include "insns/floor_w_fmt.h"
-          }
-          break;
-        case 24:
-          {
-            #include "insns/mfc1.h"
-          }
-          break;
-        case 25:
-          {
-            #include "insns/dmfc1.h"
-          }
-          break;
-        case 26:
-          {
-            #include "insns/cfc1.h"
-          }
-          break;
-        case 27:
-          {
-            #include "insns/mfhc1.h"
-          }
-          break;
-        case 28:
-          {
-            #include "insns/mtc1.h"
-          }
-          break;
-        case 29:
-          {
-            #include "insns/dmtc1.h"
-          }
-          break;
-        case 30:
-          {
-            #include "insns/ctc1.h"
-          }
-          break;
-        case 31:
-          {
-            #include "insns/mthc1.h"
-          }
-          break;
-        case 32:
-          {
-            #include "insns/cvt_s_fmt.h"
-          }
-          break;
-        case 33:
-          {
-            #include "insns/cvt_d_fmt.h"
-          }
-          break;
-        case 36:
-          {
-            #include "insns/cvt_w_fmt.h"
-          }
-          break;
-        case 37:
-          {
-            #include "insns/cvt_l_fmt.h"
-          }
-          break;
-        case 48:
-          {
-            #include "insns/c_f_fmt.h"
-          }
-          break;
-        case 49:
-          {
-            #include "insns/c_un_fmt.h"
-          }
-          break;
-        case 50:
-          {
-            #include "insns/c_eq_fmt.h"
-          }
-          break;
-        case 51:
-          {
-            #include "insns/c_ueq_fmt.h"
-          }
-          break;
-        case 52:
-          {
-            #include "insns/c_olt_fmt.h"
-          }
-          break;
-        case 53:
-          {
-            #include "insns/c_ult_fmt.h"
-          }
-          break;
-        case 54:
-          {
-            #include "insns/c_ole_fmt.h"
-          }
-          break;
-        case 55:
-          {
-            #include "insns/c_ule_fmt.h"
-          }
-          break;
-        case 56:
-          {
-            #include "insns/c_sf_fmt.h"
-          }
-          break;
-        case 57:
-          {
-            #include "insns/c_ngle_fmt.h"
-          }
-          break;
-        case 58:
-          {
-            #include "insns/c_seq_fmt.h"
-          }
-          break;
-        case 59:
-          {
-            #include "insns/c_ngl_fmt.h"
-          }
-          break;
-        case 60:
-          {
-            #include "insns/c_lt_fmt.h"
-          }
-          break;
-        case 61:
-          {
-            #include "insns/c_nge_fmt.h"
-          }
-          break;
-        case 62:
-          {
-            #include "insns/c_le_fmt.h"
-          }
-          break;
-        case 63:
-          {
-            #include "insns/c_ngt_fmt.h"
-          }
-          break;
-        default:
-          {
-            #include "insns/unimp.h"
-          }
+      case 0x0:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2000000)
+        {
+          #include "insns/round_l_fmt.h"
           break;
         }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2001000)
+        {
+          #include "insns/trunc_l_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2002000)
+        {
+          #include "insns/ceil_l_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2003000)
+        {
+          #include "insns/floor_l_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2004000)
+        {
+          #include "insns/round_w_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2005000)
+        {
+          #include "insns/trunc_w_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2006000)
+        {
+          #include "insns/ceil_w_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd2007000)
+        {
+          #include "insns/floor_w_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 20:
-    {
-      #include "insns/blt.h"
-    }
-    break;
-  case 21:
-    {
-      #include "insns/bltu.h"
-    }
-    break;
-  case 22:
-    {
-      #include "insns/ble.h"
-    }
-    break;
-  case 23:
-    {
-      #include "insns/bleu.h"
-    }
-    break;
-  case 24:
-    {
-      #include "insns/daddi.h"
-    }
-    break;
-  case 32:
-    {
-      #include "insns/lb.h"
-    }
-    break;
-  case 33:
+  }
+  case 0x6a:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/lh.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4000000)
+        {
+          #include "insns/mfc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4001000)
+        {
+          #include "insns/dmfc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4002000)
+        {
+          #include "insns/cfc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4003000)
+        {
+          #include "insns/mfhc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4004000)
+        {
+          #include "insns/mtc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4005000)
+        {
+          #include "insns/dmtc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4006000)
+        {
+          #include "insns/ctc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe007fff) == 0xd4007000)
+        {
+          #include "insns/mthc1.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 35:
+  }
+  case 0x6b:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/lw.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd6000000)
+        {
+          #include "insns/cvt_s_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd6001000)
+        {
+          #include "insns/cvt_d_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd6004000)
+        {
+          #include "insns/cvt_w_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe0ffc00) == 0xd6005000)
+        {
+          #include "insns/cvt_l_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 36:
+  }
+  case 0x6c:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/lbu.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8000000)
+        {
+          #include "insns/c_f_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8001000)
+        {
+          #include "insns/c_un_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8002000)
+        {
+          #include "insns/c_eq_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8003000)
+        {
+          #include "insns/c_ueq_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8004000)
+        {
+          #include "insns/c_olt_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8005000)
+        {
+          #include "insns/c_ult_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8006000)
+        {
+          #include "insns/c_ole_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe007c00) == 0xd8007000)
+        {
+          #include "insns/c_ule_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 37:
+  }
+  case 0x6d:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/lhu.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda000000)
+        {
+          #include "insns/c_sf_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda001000)
+        {
+          #include "insns/c_ngle_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda002000)
+        {
+          #include "insns/c_seq_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda003000)
+        {
+          #include "insns/c_ngl_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda004000)
+        {
+          #include "insns/c_lt_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda005000)
+        {
+          #include "insns/c_nge_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda006000)
+        {
+          #include "insns/c_le_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe007c00) == 0xda007000)
+        {
+          #include "insns/c_ngt_fmt.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 39:
-    {
-      #include "insns/lwu.h"
-    }
+  }
+  case 0x71:
+  {
+    #include "insns/lui.h"
     break;
-  case 40:
-    {
-      #include "insns/sb.h"
-    }
+  }
+  case 0x72:
+  {
+    #include "insns/slori.h"
     break;
-  case 41:
+  }
+  case 0x73:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/sh.h"
+      case 0x0:
+      {
+        #include "insns/beq.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/bne.h"
+        break;
+      }
+      case 0x2:
+      {
+        #include "insns/blt.h"
+        break;
+      }
+      case 0x3:
+      {
+        #include "insns/bltu.h"
+        break;
+      }
+      case 0x4:
+      {
+        #include "insns/ble.h"
+        break;
+      }
+      case 0x5:
+      {
+        #include "insns/bleu.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 43:
+  }
+  case 0x74:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/sw.h"
+      case 0x0:
+      {
+        #include "insns/addi.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/daddi.h"
+        break;
+      }
+      case 0x2:
+      {
+        #include "insns/slti.h"
+        break;
+      }
+      case 0x3:
+      {
+        #include "insns/sltiu.h"
+        break;
+      }
+      case 0x4:
+      {
+        #include "insns/andi.h"
+        break;
+      }
+      case 0x5:
+      {
+        #include "insns/ori.h"
+        break;
+      }
+      case 0x6:
+      {
+        #include "insns/xori.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 49:
+  }
+  case 0x75:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/l_s.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xea0000e0)
+        {
+          #include "insns/nor.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea000060)
+        {
+          #include "insns/sltu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea0000c0)
+        {
+          #include "insns/xor.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea000020)
+        {
+          #include "insns/sub.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea0000a0)
+        {
+          #include "insns/or.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea000000)
+        {
+          #include "insns/add.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea000040)
+        {
+          #include "insns/slt.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea000080)
+        {
+          #include "insns/and.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xea001000)
+        {
+          #include "insns/mul.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea001080)
+        {
+          #include "insns/div.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea0010c0)
+        {
+          #include "insns/rem.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea001040)
+        {
+          #include "insns/mulh.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea0010e0)
+        {
+          #include "insns/remu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea001060)
+        {
+          #include "insns/mulhu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea0010a0)
+        {
+          #include "insns/divu.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xea004040)
+        {
+          #include "insns/srlv.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea004020)
+        {
+          #include "insns/sllv.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xea004060)
+        {
+          #include "insns/srav.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfff07c00) == 0xea005000)
+        {
+          #include "insns/sll.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfff07c00) == 0xea006000)
+        {
+          #include "insns/srl.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfff07c00) == 0xea007000)
+        {
+          #include "insns/sra.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 53:
+  }
+  case 0x76:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/l_d.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xec000020)
+        {
+          #include "insns/dsub.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec000000)
+        {
+          #include "insns/dadd.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xec0010e0)
+        {
+          #include "insns/dremu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec001080)
+        {
+          #include "insns/ddiv.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec0010c0)
+        {
+          #include "insns/drem.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec001060)
+        {
+          #include "insns/dmulhu.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec001000)
+        {
+          #include "insns/dmul.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec001040)
+        {
+          #include "insns/dmulh.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec0010a0)
+        {
+          #include "insns/ddivu.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007fe0) == 0xec004020)
+        {
+          #include "insns/dsllv.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec004060)
+        {
+          #include "insns/dsrav.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xec004040)
+        {
+          #include "insns/dsrlv.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfff07c00) == 0xec005000)
+        {
+          #include "insns/dsll.h"
+          break;
+        }
+        if((insn.bits & 0xfff07c00) == 0xec005400)
+        {
+          #include "insns/dsll32.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfff07c00) == 0xec006400)
+        {
+          #include "insns/dsrl32.h"
+          break;
+        }
+        if((insn.bits & 0xfff07c00) == 0xec006000)
+        {
+          #include "insns/dsrl.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfff07c00) == 0xec007400)
+        {
+          #include "insns/dsra32.h"
+          break;
+        }
+        if((insn.bits & 0xfff07c00) == 0xec007000)
+        {
+          #include "insns/dsra.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 55:
+  }
+  case 0x78:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/ld.h"
+      case 0x0:
+      {
+        #include "insns/lb.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/lh.h"
+        break;
+      }
+      case 0x2:
+      {
+        #include "insns/lw.h"
+        break;
+      }
+      case 0x3:
+      {
+        #include "insns/ld.h"
+        break;
+      }
+      case 0x4:
+      {
+        #include "insns/lbu.h"
+        break;
+      }
+      case 0x5:
+      {
+        #include "insns/lhu.h"
+        break;
+      }
+      case 0x6:
+      {
+        #include "insns/lwu.h"
+        break;
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfff07000) == 0xf0007000)
+        {
+          #include "insns/synci.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 57:
+  }
+  case 0x79:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/s_s.h"
+      case 0x0:
+      {
+        #include "insns/sb.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/sh.h"
+        break;
+      }
+      case 0x2:
+      {
+        #include "insns/sw.h"
+        break;
+      }
+      case 0x3:
+      {
+        #include "insns/sd.h"
+        break;
+      }
+      case 0x4:
+      {
+        #include "insns/l_s.h"
+        break;
+      }
+      case 0x5:
+      {
+        #include "insns/l_d.h"
+        break;
+      }
+      case 0x6:
+      {
+        #include "insns/s_s.h"
+        break;
+      }
+      case 0x7:
+      {
+        #include "insns/s_d.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 61:
+  }
+  case 0x7b:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/s_d.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe0fffe0) == 0xf6000000)
+        {
+          #include "insns/jalr_c.h"
+          break;
+        }
+        if((insn.bits & 0xfe0fffe0) == 0xf6000040)
+        {
+          #include "insns/jalr_j.h"
+          break;
+        }
+        if((insn.bits & 0xfe0fffe0) == 0xf6000020)
+        {
+          #include "insns/jalr_r.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xffffffe0) == 0xf6001000)
+        {
+          #include "insns/rdpc.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xfe0fffe0) == 0xf6002000)
+        {
+          #include "insns/rdhwr.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xffffffff) == 0xf6003000)
+        {
+          #include "insns/sync.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xffffffff) == 0xf6004000)
+        {
+          #include "insns/syscall.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xffffffff) == 0xf6005000)
+        {
+          #include "insns/break.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
-  case 63:
+  }
+  case 0x7e:
+  {
+    switch((insn.bits >> 0xc) & 0x7)
     {
-      #include "insns/sd.h"
+      case 0x0:
+      {
+        if((insn.bits & 0xfe0fffff) == 0xfc000000)
+        {
+          #include "insns/ei.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xfe0fffff) == 0xfc001000)
+        {
+          #include "insns/di.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xffffffff) == 0xfc002000)
+        {
+          #include "insns/eret.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x4:
+      {
+        if((insn.bits & 0xfe007fff) == 0xfc004000)
+        {
+          #include "insns/mfc0.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x5:
+      {
+        if((insn.bits & 0xfe007fff) == 0xfc005000)
+        {
+          #include "insns/dmfc0.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfe007fff) == 0xfc006000)
+        {
+          #include "insns/mtc0.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xfe007fff) == 0xfc007000)
+        {
+          #include "insns/dmtc0.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
     }
     break;
+  }
   default:
-    {
-      #include "insns/unimp.h"
-    }
-    break;
+  {
+    #include "insns/unimp.h"
   }
+}

diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index c50729fe54886d505e51872bfa8a834938e4c93d..bfbc48568ddbf707f67c57f718022f31b370199c 100644 (file)
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1,2 +1,2 @@
-RD = sext32(RS + RT);
+RC = sext32(RA + RB);
 

diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index c84299d2585cf481467922f57b63b9178c736f5d..6935ccadea8c0c76ce4f2cdff22232ef7e1631ae 100644 (file)
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1 +1 @@
-RT = sext32(RS + SIMM);
+RA = sext32(SIMM + RB);

diff --git a/riscv/insns/and.h b/riscv/insns/and.h
index b109b539b36d7875ad67dad1d59d69819fc87c04..305e5417c384bde680a9307df209a2c1ef907438 100644 (file)
--- a/riscv/insns/and.h
+++ b/riscv/insns/and.h
@@ -1 +1 @@
-RD = RS & RT;
+RC = RA & RB;

diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 669b65891e77e20d7ad3e6ebbcceef7ec16c8d45..86a045c2ff0b54da48954d0a415f41b17237fb76 100644 (file)
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RT = RS & IMM;
+RA = IMM & RB;

diff --git a/riscv/insns/beq.h b/riscv/insns/beq.h
index 3ebde2fa6c2748e1a5a0c1295f4b82dcf0426e69..320c33fa431f5bb180c2f1915afce77b5461d14b 100644 (file)
--- a/riscv/insns/beq.h
+++ b/riscv/insns/beq.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS) == cmp_trunc(RT))
+if(cmp_trunc(RA) == cmp_trunc(RB))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/ble.h b/riscv/insns/ble.h
index f5e219670dcd98c14ac5521d2bb8cf716587c776..c8547bd2c3eae1d5752e3c9c68359919f0bf96a8 100644 (file)
--- a/riscv/insns/ble.h
+++ b/riscv/insns/ble.h
@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RS)) <= sreg_t(cmp_trunc(RT)))
+if(sreg_t(cmp_trunc(RA)) <= sreg_t(cmp_trunc(RB)))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/bleu.h b/riscv/insns/bleu.h
index c2c113914510510df019a7349f67b68ca4f27959..8827d68fa7061fb0798fb9b2c1d2e0c3c78d3d8b 100644 (file)
--- a/riscv/insns/bleu.h
+++ b/riscv/insns/bleu.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS) <= cmp_trunc(RT))
+if(cmp_trunc(RA) <= cmp_trunc(RB))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h
index 1010133b23d7a50f90cb6c17950ab68a536e68aa..8d95127c8cec52fa00004e90e09cf64970d0b1fa 100644 (file)
--- a/riscv/insns/blt.h
+++ b/riscv/insns/blt.h
@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RS)) < sreg_t(cmp_trunc(RT)))
+if(sreg_t(cmp_trunc(RA)) < sreg_t(cmp_trunc(RB)))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h
index a911aea82ba65972a7d142ce18cd1183b635c59b..27deefec7953c21915e7173db1e29bf278a7ffda 100644 (file)
--- a/riscv/insns/bltu.h
+++ b/riscv/insns/bltu.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS) < cmp_trunc(RT))
+if(cmp_trunc(RA) < cmp_trunc(RB))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/bne.h b/riscv/insns/bne.h
index a97d81a621db9669d229667728c94883f954c73c..aee98f6829362fc7ee4254b0c7cac4e56761c680 100644 (file)
--- a/riscv/insns/bne.h
+++ b/riscv/insns/bne.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS) != cmp_trunc(RT))
+if(cmp_trunc(RA) != cmp_trunc(RB))
   npc = BRANCH_TARGET;

diff --git a/riscv/insns/dadd.h b/riscv/insns/dadd.h
index 13b42cea814799282550058c5f92f79363034215..746cd80678ca0b19b35cd2bb48c69feb2d1a65d9 100644 (file)
--- a/riscv/insns/dadd.h
+++ b/riscv/insns/dadd.h
@@ -1,2 +1,2 @@
 require64;
-RD = RS + RT;
+RC = RA + RB;

diff --git a/riscv/insns/daddi.h b/riscv/insns/daddi.h
index bd217a02ec70370d411d6102de5a7600a47c5ae7..b6b208dc7af74fec1be93eba21b026555a0b2cf1 100644 (file)
--- a/riscv/insns/daddi.h
+++ b/riscv/insns/daddi.h
@@ -1,2 +1,2 @@
 require64;
-RT = RS + SIMM;
+RA = SIMM + RB;

diff --git a/riscv/insns/ddiv.h b/riscv/insns/ddiv.h
index 009997eeef3d67947ff58762b980b6508dcfb9ed..f0c2d2be5742a9ec67ee1384adc0383bf203e6a3 100644 (file)
--- a/riscv/insns/ddiv.h
+++ b/riscv/insns/ddiv.h
@@ -1,2 +1,2 @@
 require64;
-RD = sreg_t(RS) / sreg_t(RT);
+RC = sreg_t(RA) / sreg_t(RB);

diff --git a/riscv/insns/ddivu.h b/riscv/insns/ddivu.h
index 40346035c8fc32d6e38c1436260187c8bd6dd04f..a4e3f4f27355d4ad4434a3a29114af762bc04618 100644 (file)
--- a/riscv/insns/ddivu.h
+++ b/riscv/insns/ddivu.h
@@ -1,2 +1,2 @@
 require64;
-RD = RS / RT;
+RC = RA / RB;

diff --git a/riscv/insns/di.h b/riscv/insns/di.h
index 50bcda97c2e6c8a3431b10cace723602832eef0a..d3c70a9ac4522a5fbc6c3c910e0388f14ceb0f2b 100644 (file)
--- a/riscv/insns/di.h
+++ b/riscv/insns/di.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr & ~SR_ET);
-RT = temp;
+RA = temp;

diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 5c028883b95c83f88cb657b0ec981a71fe9a8e92..e595c85af0c8af441552ac7fa3a7c9d84d4721a8 100644 (file)
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,2 +1,2 @@
-RD = sext32(int32_t(RS)/int32_t(RT));
+RC = sext32(int32_t(RA)/int32_t(RB));
 

diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 9ccf01891c61094409658b9b231d83849a9e59a5..68f96a5d0768bf48451c93ee5ef99c2e78f27701 100644 (file)
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,2 +1,2 @@
-RD = sext32(uint32_t(RS)/uint32_t(RT));
+RC = sext32(uint32_t(RA)/uint32_t(RB));
 

diff --git a/riscv/insns/dmfc0.h b/riscv/insns/dmfc0.h
index b905d31f2a7b70f42f3deb86cfbdb32df03981a8..7808458722cb48d4573bab9f979c12313f7c7e29 100644 (file)
--- a/riscv/insns/dmfc0.h
+++ b/riscv/insns/dmfc0.h
@@ -1,29 +1,29 @@
 require_supervisor;
 require64;
 
-switch(insn.rtype.rs)
+switch(insn.rtype.rb)
 {
   case 0:
-    RT = sr;
+    RA = sr;
     break;
   case 1:
-    RT = epc;
+    RA = epc;
     break;
   case 2:
-    RT = badvaddr;
+    RA = badvaddr;
     break;
   case 3:
-    RT = ebase;
+    RA = ebase;
     break;
 
   case 8:
-    RT = MEMSIZE >> 12;
+    RA = MEMSIZE >> 12;
     break;
 
   case 17:
-    RT = sim->get_fromhost();
+    RA = sim->get_fromhost();
     break;
 
   default:
-    RT = -1;
+    RA = -1;
 }

diff --git a/riscv/insns/dmtc0.h b/riscv/insns/dmtc0.h
index 33476057bf7c050e3ed7d714bb4384207709e68d..67195a643bee6587dc0ae0159d1241924d65d6cb 100644 (file)
--- a/riscv/insns/dmtc0.h
+++ b/riscv/insns/dmtc0.h
@@ -1,19 +1,19 @@
 require_supervisor;
 require64;
 
-switch(insn.rtype.rs)
+switch(insn.rtype.rb)
 {
   case 0:
-    set_sr(RT);
+    set_sr(RA);
     break;
   case 1:
-    epc = RT;
+    epc = RA;
     break;
   case 3:
-    ebase = RT & ~0xFFF;
+    ebase = RA & ~0xFFF;
     break;
 
   case 16:
-    sim->set_tohost(RT);
+    sim->set_tohost(RA);
     break;
 }

diff --git a/riscv/insns/dmul.h b/riscv/insns/dmul.h
index 96c4128d6584daa40ebb2efe4e0e1eaf0a41a8e0..9c81285022b4746fcf57329f5a1b82260f7b25e0 100644 (file)
--- a/riscv/insns/dmul.h
+++ b/riscv/insns/dmul.h
@@ -1,2 +1,2 @@
 require64;
-RD = RS * RT;
+RC = RA * RB;

diff --git a/riscv/insns/dmulh.h b/riscv/insns/dmulh.h
new file mode 100644 (file)
index 0000000..2d7ca4c
--- /dev/null
+++ b/riscv/insns/dmulh.h
@@ -0,0 +1,4 @@
+require64;
+int64_t rb = RA;
+int64_t ra = RB;
+RC = (int128_t(rb) * int128_t(ra)) >> 64;

diff --git a/riscv/insns/dmulhu.h b/riscv/insns/dmulhu.h
new file mode 100644 (file)
index 0000000..45e9704
--- /dev/null
+++ b/riscv/insns/dmulhu.h
@@ -0,0 +1,2 @@
+require64;
+RC = (uint128_t(RA) * uint128_t(RB)) >> 64;

diff --git a/riscv/insns/drem.h b/riscv/insns/drem.h
new file mode 100644 (file)
index 0000000..dfece43
--- /dev/null
+++ b/riscv/insns/drem.h
@@ -0,0 +1,2 @@
+require64;
+RC = sreg_t(RA) % sreg_t(RB);

diff --git a/riscv/insns/dremu.h b/riscv/insns/dremu.h
new file mode 100644 (file)
index 0000000..e8ee6b1
--- /dev/null
+++ b/riscv/insns/dremu.h
@@ -0,0 +1,2 @@
+require64;
+RC = RA % RB;

diff --git a/riscv/insns/dsll.h b/riscv/insns/dsll.h
index 405115855a934ea2a510e7e2dbefb4add3f83432..a07e038cbbfee5d84e89474a1ec68506def0e288 100644 (file)
--- a/riscv/insns/dsll.h
+++ b/riscv/insns/dsll.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT << SHAMT;
+RC = RB << SHAMT;

diff --git a/riscv/insns/dsll32.h b/riscv/insns/dsll32.h
index 679f0e2945e6798eb298768f3f196990b15216ee..cfd9ba354793b57d78ad99c8709eee1814c04949 100644 (file)
--- a/riscv/insns/dsll32.h
+++ b/riscv/insns/dsll32.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT << (32+SHAMT);
+RC = RB << (32+SHAMT);

diff --git a/riscv/insns/dsllv.h b/riscv/insns/dsllv.h
index 828e7674c184e346db4fe52b1d39b28a05cdb1f3..7e81e6b68b45a278591a6bd73ebb0e5c8613b3de 100644 (file)
--- a/riscv/insns/dsllv.h
+++ b/riscv/insns/dsllv.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT << (RS & 0x3F);
+RC = RB << (RA & 0x3F);

diff --git a/riscv/insns/dsra.h b/riscv/insns/dsra.h
index 60f9ad3feac2826faff0e1337b3d5272085e1764..19118f09236ddde51753cc6b4d17b2bbbe90331f 100644 (file)
--- a/riscv/insns/dsra.h
+++ b/riscv/insns/dsra.h
@@ -1,2 +1,2 @@
 require64;
-RD = sreg_t(RT) >> SHAMT;
+RC = sreg_t(RB) >> SHAMT;

diff --git a/riscv/insns/dsra32.h b/riscv/insns/dsra32.h
index 0a5907f63b1b7d840d0f5bb0ec0bf433bf07e4ff..001e3bdf8c16beb13d31e242674b97aabd32d883 100644 (file)
--- a/riscv/insns/dsra32.h
+++ b/riscv/insns/dsra32.h
@@ -1,2 +1,2 @@
 require64;
-RD = sreg_t(RT) >> (32+SHAMT);
+RC = sreg_t(RB) >> (32+SHAMT);

diff --git a/riscv/insns/dsrav.h b/riscv/insns/dsrav.h
index 27dba05ef9ac5796a6beb265a5e9d5c9f9adb1b8..ec6fee88a0b2c8532a1706d7339925d5d39996ec 100644 (file)
--- a/riscv/insns/dsrav.h
+++ b/riscv/insns/dsrav.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT >> (RS & 0x3F);
+RC = RB >> (RA & 0x3F);

diff --git a/riscv/insns/dsrl.h b/riscv/insns/dsrl.h
index efc69e10e87820269779bc4fd686a3532f1cfde1..47426b132bcfb1c5f585f70918b942706c778564 100644 (file)
--- a/riscv/insns/dsrl.h
+++ b/riscv/insns/dsrl.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT >> SHAMT;
+RC = RB >> SHAMT;

diff --git a/riscv/insns/dsrl32.h b/riscv/insns/dsrl32.h
index f1bc91eb9c61e7838de67482816eeebd54a2dd05..5d52dea737220b8c3f60b3522f11fdfa8989dceb 100644 (file)
--- a/riscv/insns/dsrl32.h
+++ b/riscv/insns/dsrl32.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT >> (32+SHAMT);
+RC = RB >> (32+SHAMT);

diff --git a/riscv/insns/dsrlv.h b/riscv/insns/dsrlv.h
index 27dba05ef9ac5796a6beb265a5e9d5c9f9adb1b8..ec6fee88a0b2c8532a1706d7339925d5d39996ec 100644 (file)
--- a/riscv/insns/dsrlv.h
+++ b/riscv/insns/dsrlv.h
@@ -1,2 +1,2 @@
 require64;
-RD = RT >> (RS & 0x3F);
+RC = RB >> (RA & 0x3F);

diff --git a/riscv/insns/dsub.h b/riscv/insns/dsub.h
index 1c6f1c03c6f4ab9e2e970b8fc9bd88449e7db812..e7ac407639435d582f7aa08ad9b08a27e0d19e54 100644 (file)
--- a/riscv/insns/dsub.h
+++ b/riscv/insns/dsub.h
@@ -1,2 +1,2 @@
 require64;
-RD = RS - RT;
+RC = RA - RB;

diff --git a/riscv/insns/ei.h b/riscv/insns/ei.h
index 6d13be0d1dec960392435f3a9fa35f1502b43d32..ca3586f7e0f35af3d03b2de5cc8a2fbbf571df2d 100644 (file)
--- a/riscv/insns/ei.h
+++ b/riscv/insns/ei.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr | SR_ET);
-RT = temp;
+RA = temp;

diff --git a/riscv/insns/jalr_c.h b/riscv/insns/jalr_c.h
new file mode 100644 (file)
index 0000000..18b2508
--- /dev/null
+++ b/riscv/insns/jalr_c.h
@@ -0,0 +1,3 @@
+uint32_t temp = npc;
+npc = RA;
+RC = temp;

diff --git a/riscv/insns/jalr_j.h b/riscv/insns/jalr_j.h
new file mode 100644 (file)
index 0000000..5e9bb49
--- /dev/null
+++ b/riscv/insns/jalr_j.h
@@ -0,0 +1 @@
+#include "jalr_c.h"

diff --git a/riscv/insns/jalr_r.h b/riscv/insns/jalr_r.h
new file mode 100644 (file)
index 0000000..5e9bb49
--- /dev/null
+++ b/riscv/insns/jalr_r.h
@@ -0,0 +1 @@
+#include "jalr_c.h"

diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index ed1c100192b9483c73fff2f50a3599bb44d76635..ac8bf6486307d693e5d7d156a52cbeabdb29a2c9 100644 (file)
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RT = mmu.load_int8(RS+SIMM);
+RA = mmu.load_int8(RB+SIMM);

diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index 020fd19407bdcc5b6c453623de24e219ed40b42b..522eb8f98c16c92bffe61a6e314941b589aeb587 100644 (file)
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RT = mmu.load_uint8(RS+SIMM);
+RA = mmu.load_uint8(RB+SIMM);

diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 45bbcc2ff19099a347503d8013a13326cfee9932..241af6a1acb19e48bd93bad03d1b3ab5ef847be5 100644 (file)
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require64;
-RT = mmu.load_int64(RS+SIMM);
+RA = mmu.load_int64(RB+SIMM);

diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index f0ef500e216d66bcd47cb8a9ede9037196a8f528..e46ee1472edc0cd53e4ea2b66ac823a3d70e4da0 100644 (file)
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-RT = mmu.load_int16(RS+SIMM);
+RA = mmu.load_int16(RB+SIMM);

diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 6d77f0489201c50522114f762bb532a8514bfb4a..1f22423b8e330ede3a84e0bc82d8b4912f137d1c 100644 (file)
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RT = mmu.load_uint16(RS+SIMM);
+RA = mmu.load_uint16(RB+SIMM);

diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h
index 0be0c9bcdb65424f2267b9af3c46ab98f6277df3..0eb14bc4010af13a49d0226cc587bf675a233d0b 100644 (file)
--- a/riscv/insns/lui.h
+++ b/riscv/insns/lui.h
@@ -1 +1 @@
-RT = IMM << 16;
+RA = sext32(BIGIMM << IMM_BITS);

diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 123b4a82cafc3d46a438707152eab0d28922855f..e1f56fefa00308e3b479b883e80fa447f022f55f 100644 (file)
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RT = mmu.load_int32(RS+SIMM);
+RA = mmu.load_int32(RB+SIMM);

diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index af7dfc9952998cb3e36e25baa7738ecd9bc73119..311292d8022ad8d29d80d2d902a216fbc1384e66 100644 (file)
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1 +1 @@
-RT = mmu.load_uint32(RS+SIMM);
+RA = mmu.load_uint32(RB+SIMM);

diff --git a/riscv/insns/mfc0.h b/riscv/insns/mfc0.h
index f57539a94a2326c49ab08fb2959db4c53e262cbd..8a0a84ae9d4b5e465b7573c68ce815136514e06d 100644 (file)
--- a/riscv/insns/mfc0.h
+++ b/riscv/insns/mfc0.h
@@ -1,28 +1,28 @@
 require_supervisor;
 
-switch(insn.rtype.rs)
+switch(insn.rtype.rb)
 {
   case 0:
-    RT = sext32(sr);
+    RA = sext32(sr);
     break;
   case 1:
-    RT = sext32(epc);
+    RA = sext32(epc);
     break;
   case 2:
-    RT = sext32(badvaddr);
+    RA = sext32(badvaddr);
     break;
   case 3:
-    RT = sext32(ebase);
+    RA = sext32(ebase);
     break;
 
   case 8:
-    RT = sext32(MEMSIZE >> 12);
+    RA = sext32(MEMSIZE >> 12);
     break;
 
   case 17:
-    RT = sext32(sim->get_fromhost());
+    RA = sext32(sim->get_fromhost());
     break;
 
   default:
-    RT = -1;
+    RA = -1;
 }

diff --git a/riscv/insns/movn.h b/riscv/insns/movn.h
index 8688b0e5bd429856f598e5ca07fce0aaef2d587e..bdf6e5f9dbe64047cefc09d098ddbf78e9e765f1 100644 (file)
--- a/riscv/insns/movn.h
+++ b/riscv/insns/movn.h
@@ -1 +1 @@
-if(RT) RD = RS;
+if(RB) RC = RA;

diff --git a/riscv/insns/movz.h b/riscv/insns/movz.h
index 35bf49897611674f0addb16300219b43a1bf4a94..45f4f0725c6ce42a13267261b1dcf79f7c6d6adc 100644 (file)
--- a/riscv/insns/movz.h
+++ b/riscv/insns/movz.h
@@ -1 +1 @@
-if(!RT) RD = RS;
+if(!RB) RC = RA;

diff --git a/riscv/insns/mtc0.h b/riscv/insns/mtc0.h
index d45d459c92caa157803113ff9121b3c007d235a4..ca593df87a5f3dd48633f9caec780b93b9b0a386 100644 (file)
--- a/riscv/insns/mtc0.h
+++ b/riscv/insns/mtc0.h
@@ -1,18 +1,18 @@
 require_supervisor;
 
-switch(insn.rtype.rs)
+switch(insn.rtype.rb)
 {
   case 0:
-    set_sr(sext32(RT));
+    set_sr(sext32(RA));
     break;
   case 1:
-    epc = sext32(RT);
+    epc = sext32(RA);
     break;
   case 3:
-    ebase = sext32(RT & ~0xFFF);
+    ebase = sext32(RA & ~0xFFF);
     break;
 
   case 16:
-    sim->set_tohost(sext32(RT));
+    sim->set_tohost(sext32(RA));
     break;
 }

diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index 3a8fa699be0df23fd117052d63192c36304c0da6..d999172c37efcdc8321e6053161ac5918f6ee3e0 100644 (file)
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1,2 +1,2 @@
-RD = sext32(RS * RT);
+RC = sext32(RA * RB);
 

diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
new file mode 100644 (file)
index 0000000..90a17be
--- /dev/null
+++ b/riscv/insns/mulh.h
@@ -0,0 +1,2 @@
+RC = sext32((sreg_t(RA) * sreg_t(RB)) >> 32);
+

diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
new file mode 100644 (file)
index 0000000..9f3de3f
--- /dev/null
+++ b/riscv/insns/mulhu.h
@@ -0,0 +1,2 @@
+RC = sext32((RA * RB) >> 32);
+

diff --git a/riscv/insns/nor.h b/riscv/insns/nor.h
index 1e8fa52c01a7f752a644227509673b2e3b4531df..5bb7e897f02332f3aad0ab60eef0be773867fd66 100644 (file)
--- a/riscv/insns/nor.h
+++ b/riscv/insns/nor.h
@@ -1 +1 @@
-RD = ~(RS | RT);
+RC = ~(RA | RB);

diff --git a/riscv/insns/or.h b/riscv/insns/or.h
index daee005863e5e714a395a9dee0741fb3965d8bcf..d88c9f84e7c2c97856ec83b4f436af12c7d85920 100644 (file)
--- a/riscv/insns/or.h
+++ b/riscv/insns/or.h
@@ -1 +1 @@
-RD = RS | RT;
+RC = RA | RB;

diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h
index cfcf9e01fc9ce564571e04f6ee3c79e30a01a01e..2fab93710a0cff44f3648cb3af4992b43646f331 100644 (file)
--- a/riscv/insns/ori.h
+++ b/riscv/insns/ori.h
@@ -1 +1 @@
-RT = RS | IMM;
+RA = IMM | RB;

diff --git a/riscv/insns/rdpc.h b/riscv/insns/rdpc.h
new file mode 100644 (file)
index 0000000..95e528a
--- /dev/null
+++ b/riscv/insns/rdpc.h
@@ -0,0 +1 @@
+RC = npc;

diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
new file mode 100644 (file)
index 0000000..1bb3051
--- /dev/null
+++ b/riscv/insns/rem.h
@@ -0,0 +1,2 @@
+RC = sext32(int32_t(RA) % int32_t(RB));
+

diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
new file mode 100644 (file)
index 0000000..d028488
--- /dev/null
+++ b/riscv/insns/remu.h
@@ -0,0 +1,2 @@
+RC = sext32(uint32_t(RA) % uint32_t(RB));
+

diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
index f70b2eff213c860a78d20a8b0c6ea53b7e6f1918..618140d3b03fca8c619809ba6fd41b3c78f01974 100644 (file)
--- a/riscv/insns/sb.h
+++ b/riscv/insns/sb.h
@@ -1 +1 @@
-mmu.store_uint8(RS+SIMM, RT);
+mmu.store_uint8(RB+SIMM, RA);

diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index 03e64169cb4482ea8e961221c2ad8e91e46ed602..6a698ee8f7e34942c9685cc8f066ea47c95ba819 100644 (file)
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
 require64;
-mmu.store_uint64(RS+SIMM, RT);
+mmu.store_uint64(RB+SIMM, RA);

diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
index 72e24cc6b76602229119681e50ccd484756cad17..e0fdc0a4070fa5a65d38de769c41a8ad437523a4 100644 (file)
--- a/riscv/insns/sh.h
+++ b/riscv/insns/sh.h
@@ -1 +1 @@
-mmu.store_uint16(RS+SIMM, RT);
+mmu.store_uint16(RB+SIMM, RA);

diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index fe32e895f1e81fdb01142b82555eaf55c5a6ecb2..67e6809cafd3169a866da9d38e1eba56de6c174a 100644 (file)
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1 +1 @@
-RD = sext32(RT << SHAMT);
+RC = sext32(RB << SHAMT);

diff --git a/riscv/insns/sllv.h b/riscv/insns/sllv.h
index eab16525b23030821f5296195d4505abecb126aa..f694a2ff3ce019a24881f8d528c200f08107ecfe 100644 (file)
--- a/riscv/insns/sllv.h
+++ b/riscv/insns/sllv.h
@@ -1 +1 @@
-RD = sext32(RT << (RS & 0x1F));
+RC = sext32(RB << (RA & 0x1F));

diff --git a/riscv/insns/slori.h b/riscv/insns/slori.h
new file mode 100644 (file)
index 0000000..732091b
--- /dev/null
+++ b/riscv/insns/slori.h
@@ -0,0 +1 @@
+RA = (RA << 32) | (BIGIMM << IMM_BITS);

diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index 62f8684c568c9191af5c1c7623631a8eab4cf0e8..ccc1d447ea6deac67f9aedf67af49d2b02918153 100644 (file)
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-RD = sreg_t(cmp_trunc(RS)) < sreg_t(cmp_trunc(RT));
+RC = sreg_t(cmp_trunc(RA)) < sreg_t(cmp_trunc(RB));

diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 6de88a5e2a45adcd6462a1e2ab548469bf5bc89f..a5ef31ed09d5572306411ae4f89ba375b12b0f9f 100644 (file)
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-RT = sreg_t(cmp_trunc(RS)) < sreg_t(cmp_trunc(SIMM));
+RA = sreg_t(cmp_trunc(RB)) < sreg_t(cmp_trunc(SIMM));

diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index 3b6390f5d7acfb92eab8b7319724c86cb90cbe7e..a09f3ecb5572d38a9ebd5db76e2a640b786f197c 100644 (file)
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-RT = cmp_trunc(RS) < cmp_trunc(SIMM);
+RA = cmp_trunc(RB) < cmp_trunc(SIMM);

diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h
index 66873164582d20c499fe2842df34d0406b5f09a1..32fc94d3b05967752e0a41b75bfc4af2b76d1a05 100644 (file)
--- a/riscv/insns/sltu.h
+++ b/riscv/insns/sltu.h
@@ -1 +1 @@
-RD = cmp_trunc(RS) < cmp_trunc(RT);
+RC = cmp_trunc(RA) < cmp_trunc(RB);

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index ef43a4e327bc75e6538176a52dadd93e80a893ae..c2decb99b2e64148540c9a12c17f6021b433721c 100644 (file)
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1 +1 @@
-RD = sext32(sreg_t(RT) >> SHAMT);
+RC = sext32(sreg_t(RB) >> SHAMT);

diff --git a/riscv/insns/srav.h b/riscv/insns/srav.h
index a07fc5677a468f9214394b8f982702177bd25222..8e9aa8825f14dd27ffccb400ad539282fa940ea0 100644 (file)
--- a/riscv/insns/srav.h
+++ b/riscv/insns/srav.h
@@ -1 +1 @@
-RD = sext32(sreg_t(RT) >> (RS & 0x1F));
+RC = sext32(sreg_t(RB) >> (RA & 0x1F));

diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index 98958967f18e2f69b53a58619b4550fa0d2fb25f..0537a1cc5e6e9d2b903d0cd8f28bbb9d104e8265 100644 (file)
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1 +1 @@
-RD = sext32(RT >> SHAMT);
+RC = sext32(RB >> SHAMT);

diff --git a/riscv/insns/srlv.h b/riscv/insns/srlv.h
index 931d43a6146532cb360b626628d81ce763c50766..7e1755ffc468931077dc791bae0101a9986d9bfb 100644 (file)
--- a/riscv/insns/srlv.h
+++ b/riscv/insns/srlv.h
@@ -1 +1 @@
-RD = sext32(RT >> (RS & 0x1F));
+RC = sext32(RB >> (RA & 0x1F));

diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h
index 0618fb879faa4ae1bb02cc80d0c2619150497189..60bcf27befc5603c0f4a1c19fbfeebba539f0292 100644 (file)
--- a/riscv/insns/sub.h
+++ b/riscv/insns/sub.h
@@ -1,2 +1,2 @@
-RD = sext32(RS - RT);
+RC = sext32(RA - RB);
 

diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h
index 7e9fff8c3bb00f83833dbd3f89447d9d9767ecd1..b4e3b3d7b4c171cc90e6f744bf7235beee774af5 100644 (file)
--- a/riscv/insns/sw.h
+++ b/riscv/insns/sw.h
@@ -1 +1 @@
-mmu.store_uint32(RS+SIMM, RT);
+mmu.store_uint32(RB+SIMM, RA);

diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h
index 66896f4c5ee8fd431a0abb3b2325c7ba696ac44c..9d024472359e340b3f5083aa366263d3a71bb7e6 100644 (file)
--- a/riscv/insns/xor.h
+++ b/riscv/insns/xor.h
@@ -1 +1 @@
-RD = RS ^ RT;
+RC = RA ^ RB;

diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h
index 4814c5beabbfab9f276d7342fe481bf5762d6f6b..5ca46377d7386f9ba59e10d6660906c38928c0a2 100644 (file)
--- a/riscv/insns/xori.h
+++ b/riscv/insns/xori.h
@@ -1 +1 @@
-RT = RS ^ IMM;
+RA = IMM ^ RB;

diff --git a/riscv/mmu.h b/riscv/mmu.h
index 46ddd3b557f1d410218a0e775003f1017c4cac08..eea26bb66c3bf66dbb25e0f7c649b13d750b6b62 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -4,7 +4,7 @@
 class mmu_t
 {
 public:
-  mmu_t(char* _mem, size_t _memsz) : mem(_mem), memsz(_memsz) {}
+  mmu_t(char* _mem, size_t _memsz) : mem(_mem), memsz(_memsz), badvaddr(0) {}
 
   #define load_func(type) \
     type##_t load_##type(reg_t addr) { \

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 23761d3cec2b54c5f13dfd672e9c325f5b51d632..ad8ee67b32a7ed3fd073abd44d8f2577c98a001c 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -18,6 +18,9 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   set_sr(SR_S);
 
   memset(counters,0,sizeof(counters));
+
+  static_assert(sizeof(insn_t) == 4);
+  static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16);
 }
 
 void processor_t::init(uint32_t _id)
@@ -45,8 +48,6 @@ void processor_t::step(size_t n, bool noisy)
     {
       insn_t insn = mmu.load_insn(pc);
   
-      int opcode = insn.rtype.opcode;
-      int funct = insn.rtype.funct;
       reg_t npc = pc+sizeof(insn);
 
       if(noisy)