(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 5ded5ded2d29487b7d3d8a2a1e648e1d03d69d9c..47556095e5306113ce2a0ff96a26df9afe2f18ab 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -81,7 +81,8 @@ behaviour*)
 In Vertical-First Mode, the `ALL` bit still applies, but to the elements
 that are executed up to the Hint length, in parallel batches. Contrast
 this with Horizontal-First Mode which tests elements from
-`0..VL-1`, Vertical-First tests elements `srcstep..MIN(srcstep+VFHint,VL-1)` See
+`0..VL-1`, Vertical-First tests elements
+`srcstep..MIN(srcstep+VFHint-1,VL-1)`. See
 [[sv/setvl]] for the definition of Vertical-First Hint.
 
 Predication in both INT and CR modes may be applied to `sv.bc` and other