add more interfaces

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 4c69326e6a06c4e5f6ebbf7ba40e70c22a22dfea..6c49804981f12b48e32675439e01a2b66e1772b0 100644 (file)
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -220,6 +220,12 @@ List of Interfaces:
 * [[SPI]]
 * SD/MMC and eMMC [[sdmmc]]
 * Pin Multiplexing [[pinmux]]
+* Gigabit Ethernet [[RGMII]]
+
+List of Internal Interfaces:
+
+* [[AXI]]
+* [[wishbone]]
 
 # Items requiring clarification, or proposals TBD
 

diff --git a/shakti/m_class/AXI.mdwn b/shakti/m_class/AXI.mdwn
new file mode 100644 (file)
index 0000000..534538b
--- /dev/null
+++ b/shakti/m_class/AXI.mdwn
@@ -0,0 +1,6 @@
+# AXI Bridge
+
+See also [[wishbone]] Bus
+
+*
+* <https://github.com/alexforencich/verilog-axis>

diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
new file mode 100644 (file)
index 0000000..8606bac
--- /dev/null
+++ b/shakti/m_class/wishbone.mdwn
@@ -0,0 +1,6 @@
+# Wishbone Bridge
+
+See also [[AXI]] Bus
+
+*
+* <https://github.com/alexforencich/verilog-wishbone>