}
case nir_op_flt:
+ case nir_op_fge:
+ case nir_op_feq:
+ case nir_op_fne: {
+ fs_reg dest = result;
+ if (nir_src_bit_size(instr->src[0].src) > 32) {
+ dest = bld.vgrf(BRW_REGISTER_TYPE_DF, 1);
+ }
+ brw_conditional_mod cond;
+ switch (instr->op) {
+ case nir_op_flt:
+ cond = BRW_CONDITIONAL_L;
+ break;
+ case nir_op_fge:
+ cond = BRW_CONDITIONAL_GE;
+ break;
+ case nir_op_feq:
+ cond = BRW_CONDITIONAL_Z;
+ break;
+ case nir_op_fne:
+ cond = BRW_CONDITIONAL_NZ;
+ break;
+ default:
+ unreachable("bad opcode");
+ }
+ bld.CMP(dest, op[0], op[1], cond);
+ if (nir_src_bit_size(instr->src[0].src) > 32) {
+ bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));
+ }
+ break;
+ }
+
case nir_op_ilt:
case nir_op_ult:
bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_L);
break;
- case nir_op_fge:
case nir_op_ige:
case nir_op_uge:
bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_GE);
break;
- case nir_op_feq:
case nir_op_ieq:
bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_Z);
break;
- case nir_op_fne:
case nir_op_ine:
bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_NZ);
break;