* mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for

        a data/address register that appears in register field 0
        and register field 1.
        (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN

Hacking Matsushita again.  Yippie!

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fc6d5481cc73bb0d758157fb122703e5bd713171..26159c6a9fcc817957f13bdc4e33e6d914856234 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+Mon Nov  4 12:50:40 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for
+       a data/address register that appears in register field 0
+       and register field 1.
+       (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN
+
 Fri Nov  1 10:29:11 1996  Richard Henderson  <rth@tamu.edu>
 
        * alpha-dis.c (print_insn_alpha): Use new NOPAL mask for

diff --git a/opcodes/mn10300-opc.c b/opcodes/mn10300-opc.c
index 6795eac2e292955cfac019dbd298c06a8fdd3684..2afa3e755179bfade0ebdf740e43babac575c200 100644 (file)
--- a/opcodes/mn10300-opc.c
+++ b/opcodes/mn10300-opc.c
@@ -100,6 +100,13 @@ const struct mn10300_operand mn10300_operands[] = {
 
 #define PAREN  (SIMM16+1)
   {0, 0, MN10300_OPERAND_PAREN}, 
+
+#define DN01     (PAREN+1)
+  {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
+
+#define AN01     (DN01+1)
+  {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
+
 } ; 
 
 #define MEM(ADDR) PAREN, ADDR, PAREN 
@@ -123,11 +130,11 @@ const struct mn10300_operand mn10300_operands[] = {
    sorted by major opcode.  */
 
 const struct mn10300_opcode mn10300_opcodes[] = {
-{ "mov",       0x8000,         0xf000,         FMT_S1, {SIMM8, DN0}},
+{ "mov",       0x8000,         0xf000,         FMT_S1, {SIMM8, DN01}},
 { "mov",       0x80,           0xf0,           FMT_S0, {DM1, DN0}},
 { "mov",       0xf1e0,         0xfff0,         FMT_D0, {DM1, AN0}},
 { "mov",       0xf1d0,         0xfff0,         FMT_D0, {AM1, DN0}},
-{ "mov",       0x9000,         0xf000,         FMT_S1, {IMM8, AN0}},
+{ "mov",       0x9000,         0xf000,         FMT_S1, {IMM8, AN01}},
 { "mov",       0x90,           0xf0,           FMT_S0, {AM1, AN0}},
 { "mov",       0x3c,           0xfc,           FMT_S0, {SP, AN0}},
 { "mov",       0xf2f0,         0xfff3,         FMT_D0, {AM1, SP}},
@@ -268,11 +275,11 @@ const struct mn10300_opcode mn10300_opcodes[] = {
 { "inc",       0x41,           0xf3,           FMT_S0, {AN1}},
 { "inc4",      0x50,           0xfc,           FMT_S0, {AN0}},
 
-{ "cmp",       0xa000,         0xf000,         FMT_S1, {SIMM8, DN0}},
+{ "cmp",       0xa000,         0xf000,         FMT_S1, {SIMM8, DN01}},
 { "cmp",       0xa0,           0xf0,           FMT_S0, {DM1, DN0}},
 { "cmp",       0xf1a0,         0xfff0,         FMT_D0, {DM1, AN0}},
 { "cmp",       0xf190,         0xfff0,         FMT_D0, {AM1, DN0}},
-{ "cmp",       0xb000,         0xf000,         FMT_S1, {IMM8, AN0}},
+{ "cmp",       0xb000,         0xf000,         FMT_S1, {IMM8, AN01}},
 { "cmp",       0xb0,           0xf0,           FMT_S0, {AM1, AN0}},
 { "cmp",       0xfac80000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
 { "cmp",       0xfcc80000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},