+Sun Dec 6 00:28:16 1998 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
+
+ * config/c4x/c4x.c (valid_parallel_load_store): Flog functionality
+ from old valid_parallel_operands_4.
+ (valid_parallel_operands_4): Check that operands for 4 operand
+ parallel insns are valid, excluding load/store insns.
+ * config/c4x/c4x.h (valid_parallel_load_store): Add prototype.
+ * config/c4x/c4x.md (*movqf_parallel, *movqi_parallel): Use
+ valid_parallel_load_store instead of valid_parallel_operands_4.
+ (*absqf2_movqf_clobber, *floatqiqf2_movqf_clobber,
+ *negqf2_movqf_clobber, *absqi2_movqi_clobber,
+ *fixqfqi2_movqi_clobber, *negqi2_movqi_clobber,
+ *notqi_movqi_clobber): Use valid_parallel_operands_4.
+ (*subqf3_movqf_clobber, *ashlqi3_movqi_clobber,
+ *ashrqi3_movqi_clobber, *lshrqi3_movqi_clobber,
+ *subqi3_movqi_clobber): Use valid_parallel_operands_5.
+
Sat Dec 5 23:52:01 1998 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
* config/c4x/c4x.c (iteration_info): Delete extern.
/* Validate combination of operands for parallel load/store instructions. */
-int
-valid_parallel_operands_4 (operands, mode)
+valid_parallel_load_store (operands, mode)
rtx *operands;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
should be REGs and the other 2 should be MEMs. */
/* This test prevents the multipack pass from using this pattern if
- op0 is used as an index or base register in op3, since this combination
- will require reloading. */
+ op0 is used as an index or base register in op2 or op3, since
+ this combination will require reloading. */
if (GET_CODE (op0) == REG
- && GET_CODE (op3) == MEM
- && reg_mentioned_p (op0, XEXP (op3, 0)))
+ && ((GET_CODE (op2) == MEM && reg_mentioned_p (op0, XEXP (op2, 0)))
+ || (GET_CODE (op3) == MEM && reg_mentioned_p (op0, XEXP (op3, 0)))))
return 0;
/* LDI||LDI */
}
-/* We only use this to check operands 1 and 2 since these may be
- commutative. It will need extending for the C32 opcodes. */
+int
+valid_parallel_operands_4 (operands, mode)
+ rtx *operands;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+ int regs = 0;
+ rtx op0 = operands[0];
+ rtx op2 = operands[2];
+
+ if (GET_CODE (op0) == SUBREG)
+ op0 = SUBREG_REG (op0);
+ if (GET_CODE (op2) == SUBREG)
+ op2 = SUBREG_REG (op2);
+
+ /* This test prevents the multipack pass from using this pattern if
+ op0 is used as an index or base register in op2, since this combination
+ will require reloading. */
+ if (GET_CODE (op0) == REG
+ && GET_CODE (op2) == MEM
+ && reg_mentioned_p (op0, XEXP (op2, 0)))
+ return 0;
+
+ return 1;
+}
+
+
int
valid_parallel_operands_5 (operands, mode)
rtx *operands;
{
int regs = 0;
rtx op0 = operands[0];
+ rtx op1 = operands[1];
rtx op2 = operands[2];
rtx op3 = operands[3];
if (GET_CODE (op0) == SUBREG)
op0 = SUBREG_REG (op0);
+ if (GET_CODE (op1) == SUBREG)
+ op1 = SUBREG_REG (op1);
if (GET_CODE (op2) == SUBREG)
op2 = SUBREG_REG (op2);
/* The patterns should only allow ext_low_reg_operand() or
- par_ind_operand() operands. */
-
- if (GET_CODE (op0) == REG)
+ par_ind_operand() operands. Operands 1 and 2 may be commutative
+ but only one of them can be a register. */
+ if (GET_CODE (op1) == REG)
regs++;
if (GET_CODE (op2) == REG)
regs++;
(match_operand:QI 1 "parallel_operand" "S<>,q,S<>,q"))
(set (match_operand:QI 2 "parallel_operand" "=q,S<>,S<>,q")
(match_operand:QI 3 "parallel_operand" "S<>,q,q,S<>"))]
- "valid_parallel_operands_4 (operands, QImode)"
+ "valid_parallel_load_store (operands, QImode)"
"@
ldi1\\t%1,%0\\n||\\tldi2\\t%3,%2
sti1\\t%1,%0\\n||\\tsti2\\t%3,%2
(match_operand:QF 1 "parallel_operand" "S<>,q,S<>,q"))
(set (match_operand:QF 2 "parallel_operand" "=q,S<>,S<>,q")
(match_operand:QF 3 "parallel_operand" "S<>,q,q,S<>"))]
- "valid_parallel_operands_4 (operands, QFmode)"
+ "valid_parallel_load_store (operands, QFmode)"
"@
ldf1\\t%1,%0\\n||\\tldf2\\t%3,%2
stf1\\t%1,%0\\n||\\tstf2\\t%3,%2
(set (match_operand:QF 2 "par_ind_operand" "=S<>")
(match_operand:QF 3 "ext_low_reg_operand" "q"))
(clobber (reg:CC_NOOV 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
"absf\\t%1,%0\\n||\\tstf\\t%3,%2"
[(set_attr "type" "binarycc")])
; FLOAT/STF
;
-(define_insn "*floatqiqf_movqf_clobber"
+(define_insn "*floatqiqf2_movqf_clobber"
[(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
(float:QF (match_operand:QI 1 "par_ind_operand" "S<>")))
(set (match_operand:QF 2 "par_ind_operand" "=S<>")
(match_operand:QF 3 "ext_low_reg_operand" "q"))
(clobber (reg:CC 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
"float\\t%1,%0\\n||\\tstf\\t%3,%2"
[(set_attr "type" "binarycc")])
(set (match_operand:QF 2 "par_ind_operand" "=S<>")
(match_operand:QF 3 "ext_low_reg_operand" "q"))
(clobber (reg:CC 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
"negf\\t%1,%0\\n||\\tstf\\t%3,%2"
[(set_attr "type" "binarycc")])
(define_insn "*subqf3_movqf_clobber"
[(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
(minus:QF (match_operand:QF 1 "ext_low_reg_operand" "q")
- (match_operand:QF 2 "par_ind_operand" "S<>")))
+ (match_operand:QF 2 "par_ind_operand" "S<>")))
(set (match_operand:QF 3 "par_ind_operand" "=S<>")
(match_operand:QF 4 "ext_low_reg_operand" "q"))
(clobber (reg:CC 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
"subf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
[(set_attr "type" "binarycc")])
(set (match_operand:QI 2 "par_ind_operand" "=S<>")
(match_operand:QI 3 "ext_low_reg_operand" "q"))
(clobber (reg:CC_NOOV 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
"absi\\t%1,%0\\n||\\tsti\\t%3,%2"
[(set_attr "type" "binarycc")])
(set (match_operand:QI 3 "par_ind_operand" "=S<>")
(match_operand:QI 4 "ext_low_reg_operand" "q"))
(clobber (reg:CC 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
"ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
[(set_attr "type" "binarycc")])
; ASH(right)/STI
;
-(define_insn "*ashlqi3_movqi_clobber"
+(define_insn "*ashrqi3_movqi_clobber"
[(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
(ashiftrt:QI (match_operand:QI 1 "par_ind_operand" "S<>")
(neg:QI (match_operand:QI 2 "ext_low_reg_operand" "q"))))
(set (match_operand:QI 3 "par_ind_operand" "=S<>")
(match_operand:QI 4 "ext_low_reg_operand" "q"))
(clobber (reg:CC 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
"ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
[(set_attr "type" "binarycc")])
(set (match_operand:QI 2 "par_ind_operand" "=S<>")
(match_operand:QI 3 "ext_low_reg_operand" "q"))
(clobber (reg:CC 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
"fix\\t%1,%0\\n||\\tsti\\t%3,%2"
[(set_attr "type" "binarycc")])
(set (match_operand:QI 3 "par_ind_operand" "=S<>")
(match_operand:QI 4 "ext_low_reg_operand" "q"))
(clobber (reg:CC 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
"lsh3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
[(set_attr "type" "binarycc")])
(set (match_operand:QI 2 "par_ind_operand" "=S<>")
(match_operand:QI 3 "ext_low_reg_operand" "q"))
(clobber (reg:CC 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
"negi\\t%1,%0\\n||\\tsti\\t%3,%2"
[(set_attr "type" "binarycc")])
(set (match_operand:QI 2 "par_ind_operand" "=S<>")
(match_operand:QI 3 "ext_low_reg_operand" "q"))
(clobber (reg:CC 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
"not\\t%1,%0\\n||\\tsti\\t%3,%2"
[(set_attr "type" "binarycc")])
(set (match_operand:QI 3 "par_ind_operand" "=S<>")
(match_operand:QI 4 "ext_low_reg_operand" "q"))
(clobber (reg:CC 21))]
- "TARGET_PARALLEL"
+ "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
"subi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
[(set_attr "type" "binarycc")])