Merge with main repository.

diff --git a/configs/example/se.py b/configs/example/se.py
index 1edd99e9b6bea6bc0edf9b399116c26f953af1a0..35025a8ff27a292780610522ab5f6a3fc96a6740 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -181,7 +181,6 @@ if options.ruby:
     options.use_map = True
     Ruby.create_system(options, system)
     assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
-    system.system_port = system.ruby._sys_port_proxy.port
 else:
     system.system_port = system.membus.port
     system.physmem.port = system.membus.port

diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index b2342eed493dc7f129bef11f93d16ab64594f4dc..920eac01927a458624c96470b8a42792886dc919 100644 (file)
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -105,6 +105,10 @@ def create_system(options, system, piobus = None, dma_devices = []):
     # full-fledged controller
     system.sys_port_proxy = sys_port_proxy
 
+    # Connect the system port for loading of binaries etc
+    system.system_port = system.sys_port_proxy.port
+
+
     #
     # Set the network classes based on the command line options
     #
@@ -182,5 +186,4 @@ def create_system(options, system, piobus = None, dma_devices = []):
     ruby.profiler = ruby_profiler
     ruby.mem_size = total_mem_size
     ruby._cpu_ruby_ports = cpu_sequencers
-    ruby._sys_port_proxy = sys_port_proxy
     ruby.random_seed    = options.random_seed

diff --git a/src/arch/arm/vtophys.hh b/src/arch/arm/vtophys.hh
index a85209a4a04518f584da2738987583dcc4a67b18..12a6c6ec69bbc637836222f8eb33d6190dd3f2d2 100644 (file)
--- a/src/arch/arm/vtophys.hh
+++ b/src/arch/arm/vtophys.hh
@@ -38,7 +38,6 @@
 #include "arch/arm/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace ArmISA {
     inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }

diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh
index 37a7378a83c862c3318585bbf4e3668ef7026ab0..a3fbdd457a5191d635b55eaf6a7f6fd8bf460fbe 100644 (file)
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@ -38,7 +38,6 @@
 #include "arch/mips/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace MipsISA {
     Addr vtophys(Addr vaddr);

diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh
index a2582b296f81dc05f48cbe604f469d65ad49c1e6..51696d9b29d2111667884cd817ea42a5bb284e5f 100644 (file)
--- a/src/arch/power/vtophys.hh
+++ b/src/arch/power/vtophys.hh
@@ -40,7 +40,6 @@
 #include "arch/power/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace PowerISA {
 

diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh
index f55967b538b706e37da90c04569c4834913a15ca..7c1d23e808e4219e64ad4065dc2050e604e0c214 100644 (file)
--- a/src/arch/sparc/vtophys.hh
+++ b/src/arch/sparc/vtophys.hh
@@ -36,13 +36,9 @@
 #include "arch/sparc/pagetable.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace SparcISA {
 
-PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
-
 Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
 

diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 7fe0fb5ef117d4551fa3eca676bf1ecd38a2e21f..5a9cfce32c61d445716d2c25cb60ebfbdc4b7283 100644 (file)
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -44,8 +44,6 @@ namespace Kernel {
     class Statistics;
 };
 
-class TranslatingPort;
-
 /**
  * Derived ThreadContext class for use with the InOrderCPU.  It
  * provides the interface for any external objects to access a

diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index ff6ca00939bbb7a64fbc0d4ab88f06e570138ff9..ffe828c9456665e6e8e2a6815d31c107ffab022b 100755 (executable)
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -40,8 +40,6 @@ namespace Kernel {
     class Statistics;
 };
 
-class TranslatingPort;
-
 /**
  * Derived ThreadContext class for use with the O3CPU.  It
  * provides the interface for any external objects to access a

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index f2132dc360e81f477bffc475edde9253dc8a0143..97964c0e8c2f5262d68c73fee239546c26800d3c 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -57,8 +57,6 @@ class BaseCPU;
 
 class FunctionProfile;
 class ProfileNode;
-class PhysicalPort;
-class TranslatingPort;
 
 namespace TheISA {
     namespace Kernel {

diff --git a/src/kern/solaris/solaris.hh b/src/kern/solaris/solaris.hh
index da6ce84f78d9432bd4194ea1b365912971b0fb57..9cd5af16f7fe2a7a7fb732b5cf65bc337b8fbd74 100644 (file)
--- a/src/kern/solaris/solaris.hh
+++ b/src/kern/solaris/solaris.hh
@@ -34,8 +34,6 @@
 #include "base/types.hh"
 #include "kern/operatingsystem.hh"
 
-class TranslatingPort;
-
 ///
 /// This class encapsulates the types, structures, constants,
 /// functions, and syscall-number mappings specific to the Solaris

diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index b60ca2a073ecc531d7e1b270244432589254d70b..af414f17ace3459a7997d2d9d8c091f488cc7f29 100644 (file)
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -88,8 +88,7 @@ RubyPort::getPort(const std::string &if_name, int idx)
         // RubyPort should only have one port to physical memory
         assert (physMemPort == NULL);
 
-        physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this,
-                                 ruby_system, access_phys_mem);
+        physMemPort = new PioPort(csprintf("%s-physMemPort", name()), this);
 
         return physMemPort;
     }

diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 2ffdef3d9dc71abc0a1e49b894787c57af52e18f..6df713a13a7febf8df4f375f9eac9e063f434af4 100644 (file)
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -155,7 +155,7 @@ class RubyPort : public MemObject
     uint16_t m_port_id;
     uint64_t m_request_cnt;
 
-    M5Port* physMemPort;
+    PioPort* physMemPort;
 
     /*! Vector of CPU Port attached to this Ruby port. */
     typedef std::vector<M5Port*>::iterator CpuPortIter;

diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 52eb5290452aabfcb07857d00b50d4312308d4ca..43031dd02b3a801a97cda4bc1fda7d1622ba209c 100644 (file)
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -106,10 +106,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
      #
      ruby_port.access_phys_mem = False
 
-
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------

diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index 2f8829db0dd80d883cede28e42c482c57f4a3164..cff511bf8ae4eaf6ffb80150d32b3a00347f1b57 100644 (file)
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -46,6 +46,8 @@ for cpu in cpus:
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation

diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index b967a508043f099e5ec0749988e2b656a1efdcee..14b0ff1ab7c11deccdefd55cfb8c3a4b71643be2 100644 (file)
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -43,4 +43,7 @@ system = System(cpu = cpu,
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
+
 root = Root(full_system = False, system = system)

diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 2531a30c8e9193c3f99279d6b1a499c295a37992..116afa2b62a6653f77a155f58c25e562026be9b8 100644 (file)
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -102,9 +102,6 @@ for ruby_port in system.ruby._cpu_ruby_ports:
     #
     ruby_port.access_phys_mem = False
 
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------

diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index fe0311801cc3a4268cc5494adcb45451180de713..8b61fd1f240163b58a8764ad146ba2db15c8bd45 100644 (file)
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -47,6 +47,8 @@ for cpu in cpus:
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation

diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index c57ffd1f20bf9facd1eb029264cb4d12b09d7960..9919cabcbb258c5e83a00594d607e048ca55f358 100644 (file)
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -85,9 +85,6 @@ for (i, cpu) in enumerate(system.cpu):
     cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
     cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
 
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------

diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 46436d18c27160a3061f3c1fd72d1ae66695d85f..4f812f209533f71387ab6194de6703b082d78038 100644 (file)
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -81,9 +81,6 @@ assert(len(system.ruby._cpu_ruby_ports) == 1)
 #
 cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
 
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------