options.use_map = True
Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
- system.system_port = system.ruby._sys_port_proxy.port
else:
system.system_port = system.membus.port
system.physmem.port = system.membus.port
# full-fledged controller
system.sys_port_proxy = sys_port_proxy
+ # Connect the system port for loading of binaries etc
+ system.system_port = system.sys_port_proxy.port
+
+
#
# Set the network classes based on the command line options
#
ruby.profiler = ruby_profiler
ruby.mem_size = total_mem_size
ruby._cpu_ruby_ports = cpu_sequencers
- ruby._sys_port_proxy = sys_port_proxy
ruby.random_seed = options.random_seed
#include "arch/arm/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace ArmISA {
inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
#include "arch/mips/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace MipsISA {
Addr vtophys(Addr vaddr);
#include "arch/power/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace PowerISA {
#include "arch/sparc/pagetable.hh"
class ThreadContext;
-class FunctionalPort;
namespace SparcISA {
-PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
-
Addr vtophys(Addr vaddr);
Addr vtophys(ThreadContext *tc, Addr vaddr);
class Statistics;
};
-class TranslatingPort;
-
/**
* Derived ThreadContext class for use with the InOrderCPU. It
* provides the interface for any external objects to access a
class Statistics;
};
-class TranslatingPort;
-
/**
* Derived ThreadContext class for use with the O3CPU. It
* provides the interface for any external objects to access a
class FunctionProfile;
class ProfileNode;
-class PhysicalPort;
-class TranslatingPort;
namespace TheISA {
namespace Kernel {
#include "base/types.hh"
#include "kern/operatingsystem.hh"
-class TranslatingPort;
-
///
/// This class encapsulates the types, structures, constants,
/// functions, and syscall-number mappings specific to the Solaris
// RubyPort should only have one port to physical memory
assert (physMemPort == NULL);
- physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this,
- ruby_system, access_phys_mem);
+ physMemPort = new PioPort(csprintf("%s-physMemPort", name()), this);
return physMemPort;
}
uint16_t m_port_id;
uint64_t m_request_cnt;
- M5Port* physMemPort;
+ PioPort* physMemPort;
/*! Vector of CPU Port attached to this Ruby port. */
typedef std::vector<M5Port*>::iterator CpuPortIter;
#
ruby_port.access_phys_mem = False
-
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
# connect memory to membus
system.physmem.port = system.membus.port
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
# -----------------------
# run simulation
system.physmem.port = system.membus.port
cpu.connectAllPorts(system.membus)
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
+
root = Root(full_system = False, system = system)
#
ruby_port.access_phys_mem = False
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
# connect memory to membus
system.physmem.port = system.membus.port
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
# -----------------------
# run simulation
cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
#
cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------