Merge with main repository.

diff --cc configs/example/se.py
Simple merge

diff --cc src/arch/mips/vtophys.hh
index 37a7378a83c862c3318585bbf4e3668ef7026ab0,741ac36bc49deb2abbd6fc5faa57f113584b30cd..a3fbdd457a5191d635b55eaf6a7f6fd8bf460fbe
--- 1/src/arch/mips/vtophys.hh
--- 2/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@@ -38,9 -38,26 +38,8 @@@
  #include "arch/mips/utility.hh"
  
  class ThreadContext;
- class FunctionalPort;
  
  namespace MipsISA {
 -    inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
 -
 -    // User Virtual
 -    inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
 -
 -    inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
 -
 -    inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
 -
 -    inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
 -
 -    inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
 -
 -    inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
 -
 -    inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
 -
 -
      Addr vtophys(Addr vaddr);
      Addr vtophys(ThreadContext *tc, Addr vaddr);
  

diff --cc src/arch/power/vtophys.hh
Simple merge

diff --cc src/cpu/inorder/thread_context.hh
Simple merge

diff --cc src/cpu/o3/thread_context.hh
Simple merge

diff --cc src/cpu/simple_thread.hh
Simple merge

diff --cc src/kern/solaris/solaris.hh
index da6ce84f78d9432bd4194ea1b365912971b0fb57,c6fb93f04aff5af9c813fc6c09cd68278823f1cb..9cd5af16f7fe2a7a7fb732b5cf65bc337b8fbd74
--- 1/src/kern/solaris/solaris.hh
--- 2/src/kern/solaris/solaris.hh
+++ b/src/kern/solaris/solaris.hh
@@@ -32,10 -32,16 +32,8 @@@
  #define __SOLARIS_HH__
  
  #include "base/types.hh"
 -#include "config/full_system.hh"
 -
 -#if FULL_SYSTEM
 -
 -class Solaris {};
 -
 -#else //!FULL_SYSTEM
 -
  #include "kern/operatingsystem.hh"
  
- class TranslatingPort;
- 
  ///
  /// This class encapsulates the types, structures, constants,
  /// functions, and syscall-number mappings specific to the Solaris

diff --cc tests/configs/memtest-ruby.py
Simple merge

diff --cc tests/configs/o3-timing-mp-ruby.py
Simple merge

diff --cc tests/configs/o3-timing-ruby.py
index b967a508043f099e5ec0749988e2b656a1efdcee,3b6d58b3b9c915d3bc37b5e0395deb13c80ad1d1..14b0ff1ab7c11deccdefd55cfb8c3a4b71643be2
--- 1/tests/configs/o3-timing-ruby.py
--- 2/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@@ -43,4 -43,7 +43,7 @@@ system = System(cpu = cpu
  system.physmem.port = system.membus.port
  cpu.connectAllPorts(system.membus)
  
 -root = Root(system = system)
+ # Connect the system port for loading of binaries etc
+ system.system_port = system.membus.port
+ 
 +root = Root(full_system = False, system = system)

diff --cc tests/configs/rubytest-ruby.py
Simple merge

diff --cc tests/configs/simple-atomic-mp-ruby.py
Simple merge

diff --cc tests/configs/simple-timing-mp-ruby.py
Simple merge

diff --cc tests/configs/simple-timing-ruby.py
index 46436d18c27160a3061f3c1fd72d1ae66695d85f,1d67f6f976a6d4b9cc1780af7d114f59779280af..4f812f209533f71387ab6194de6703b082d78038
--- 1/tests/configs/simple-timing-ruby.py
--- 2/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@@ -79,11 -82,9 +79,8 @@@ assert(len(system.ruby._cpu_ruby_ports
  # Tie the cpu cache ports to the ruby cpu ports and
  # physmem, respectively
  #
 -cpu.icache_port = system.ruby._cpu_ruby_ports[0].port
 -cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port
 +cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
  
- # Connect the system port for loading of binaries etc
- system.system_port = system.ruby._sys_port_proxy.port
- 
  # -----------------------
  # run simulation
  # -----------------------