hdl.ast: add name_suffix=".." option to Signal.like().

This simplifies creation of related signals with nice names during
metaprogramming, e.g.

  def make_ff(m, sig):
      sig_ff = Signal.like(sig, name_suffix="_ff")
      m.d.sync += sig_ff.eq(sig)
      return sig_ff

diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py
index 809ff20240f7fb976d828b9c7577be728efff103..326ed54b1922ae58ba03da60b490cbd6b8b3f4d9 100644 (file)
--- a/nmigen/hdl/ast.py
+++ b/nmigen/hdl/ast.py
@@ -630,7 +630,7 @@ class Signal(Value, DUID):
         self.decoder = decoder
 
     @classmethod
-    def like(cls, other, name=None, src_loc_at=0, **kwargs):
+    def like(cls, other, name=None, name_suffix=None, src_loc_at=0, **kwargs):
         """Create Signal based on another.
 
         Parameters
@@ -638,8 +638,13 @@ class Signal(Value, DUID):
         other : Value
             Object to base this Signal on.
         """
-        name = name or tracer.get_var_name(depth=2 + src_loc_at, default="$like")
-        kw   = dict(shape=cls.wrap(other).shape(), name=name)
+        if name is not None:
+            new_name = str(name)
+        elif name_suffix is not None:
+            new_name = other.name + str(name_suffix)
+        else:
+            new_name = tracer.get_var_name(depth=2 + src_loc_at, default="$like")
+        kw = dict(shape=cls.wrap(other).shape(), name=new_name)
         if isinstance(other, cls):
             kw.update(reset=other.reset, reset_less=other.reset_less,
                       attrs=other.attrs, decoder=other.decoder)

diff --git a/nmigen/test/test_hdl_ast.py b/nmigen/test/test_hdl_ast.py
index 3983239a1da06de0a82164b08e66b35817e3650d..9fbf6375e903b6a03c980efce9035cda75cd26f6 100644 (file)
--- a/nmigen/test/test_hdl_ast.py
+++ b/nmigen/test/test_hdl_ast.py
@@ -483,6 +483,8 @@ class SignalTestCase(FHDLTestCase):
         self.assertEqual(s6.shape(), (4, False))
         s7 = [Signal.like(Signal(4))][0]
         self.assertEqual(s7.name, "$like")
+        s8 = Signal.like(s1, name_suffix="_ff")
+        self.assertEqual(s8.name, "s1_ff")
 
 
 class ClockSignalTestCase(FHDLTestCase):