bank/csrgen: interface -> bus

diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py
index 9b28904d27e6ad789bce3e64bc3870a60462c2a0..cd87316b0045a4a7b1716b17a9d172e219caee99 100644 (file)
--- a/migen/bank/csrgen.py
+++ b/migen/bank/csrgen.py
@@ -3,19 +3,17 @@ from migen.bus import csr
 from migen.bank.description import *
 
 class Bank:
-       def __init__(self, description, address=0, interface=None):
+       def __init__(self, description, address=0, bus=csr.Interface()):
                self.description = description
                self.address = address
-               if interface is None:
-                       interface = csr.Interface()
-               self.interface = interface
+               self.bus = bus
        
        def get_fragment(self):
                comb = []
                sync = []
                
                sel = Signal()
-               comb.append(sel.eq(self.interface.adr[9:] == self.address))
+               comb.append(sel.eq(self.bus.adr[9:] == self.address))
                
                desc_exp = expand_description(self.description, csr.data_width)
                nbits = bits_for(len(desc_exp)-1)
@@ -24,16 +22,16 @@ class Bank:
                bwcases = {}
                for i, reg in enumerate(desc_exp):
                        if isinstance(reg, RegisterRaw):
-                               comb.append(reg.r.eq(self.interface.dat_w[:reg.size]))
+                               comb.append(reg.r.eq(self.bus.dat_w[:reg.size]))
                                comb.append(reg.re.eq(sel & \
-                                       self.interface.we & \
-                                       (self.interface.adr[:nbits] == i)))
+                                       self.bus.we & \
+                                       (self.bus.adr[:nbits] == i)))
                        elif isinstance(reg, RegisterFields):
                                bwra = []
                                offset = 0
                                for field in reg.fields:
                                        if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
-                                               bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
+                                               bwra.append(field.storage.eq(self.bus.dat_w[offset:offset+field.size]))
                                        offset += field.size
                                if bwra:
                                        bwcases[i] = bwra
@@ -41,17 +39,17 @@ class Bank:
                                for field in reg.fields:
                                        if isinstance(field, FieldAlias) and field.commit_list:
                                                commit_instr = [hf.commit_to.eq(hf.storage) for hf in field.commit_list]
-                                               sync.append(If(sel & self.interface.we & self.interface.adr[:nbits] == i, *commit_instr))
+                                               sync.append(If(sel & self.bus.we & self.bus.adr[:nbits] == i, *commit_instr))
                        else:
                                raise TypeError
                if bwcases:
-                       sync.append(If(sel & self.interface.we, Case(self.interface.adr[:nbits], bwcases)))
+                       sync.append(If(sel & self.bus.we, Case(self.bus.adr[:nbits], bwcases)))
                
                # Bus reads
                brcases = {}
                for i, reg in enumerate(desc_exp):
                        if isinstance(reg, RegisterRaw):
-                               brcases[i] = [self.interface.dat_r.eq(reg.w)]
+                               brcases[i] = [self.bus.dat_r.eq(reg.w)]
                        elif isinstance(reg, RegisterFields):
                                brs = []
                                reg_readable = False
@@ -62,14 +60,14 @@ class Bank:
                                        else:
                                                brs.append(Replicate(0, field.size))
                                if reg_readable:
-                                       brcases[i] = [self.interface.dat_r.eq(Cat(*brs))]
+                                       brcases[i] = [self.bus.dat_r.eq(Cat(*brs))]
                        else:
                                raise TypeError
                if brcases:
-                       sync.append(self.interface.dat_r.eq(0))
-                       sync.append(If(sel, Case(self.interface.adr[:nbits], brcases)))
+                       sync.append(self.bus.dat_r.eq(0))
+                       sync.append(If(sel, Case(self.bus.adr[:nbits], brcases)))
                else:
-                       comb.append(self.interface.dat_r.eq(0))
+                       comb.append(self.bus.dat_r.eq(0))
                
                # Device access
                for reg in self.description: