(no commit message)

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 01c385156517aa910611d058ff4d4090deb850d1..770c462109bc7b06c0e91e90a9b4b55b300a1618 100644 (file)
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -102,6 +102,27 @@ Example
 
 The vmsbf.m instruction takes a mask register as input and writes results to a mask register. The instruction writes a 1 to all active mask elements before the first source element that is a 1, then writes a 0 to that element and all following active elements. If there is no set bit in the source vector, then all active elements in the destination are written with a 1.
 
+pseudocode:
+
+    def sbf(rd, rs1, rs2):
+        rd = 0
+        # start setting if no predicate or if 1st predicate bit set
+        setting_mode = rs2 == x0 or (regs[rs2] & 1)
+        while i < XLEN:
+            bit = 1<<i
+            if rs2 != x0 and (regs[rs2] & bit):
+                # reset searching
+                setting_mode = False
+            if setting_mode:
+                if regs[rs1] & bit: # found a bit in rs1: stop setting rd
+                    setting_mode = False
+                else:
+                    regs[rd] |= bit
+            else if rs2 != x0: # searching mode
+                if (regs[rs2] & bit):
+                    setting_mode = True # back into "setting" mode
+            i += 1
+
 ## sifm
 
 The vector mask set-including-first instruction is similar to set-before-first, except it also includes the element with a set bit.
@@ -125,13 +146,44 @@ The vector mask set-including-first instruction is similar to set-before-first,
                        vmsif.m v2, v3, v0.t
      1 1 x x x x 1 1   v2 contents
 
+Pseudo-code:
+
+    def sif(rd, rs1, rs2):
+        rd = 0
+        setting_mode = rs2 == x0 or (regs[rs2] & 1)
+
+        while i < XLEN:
+            bit = 1<<i
+
+            # only reenable when predicate in use, and bit valid
+            if !setting_mode && rs2 != x0:
+                if (regs[rs2] & bit):
+                    # back into "setting" mode
+                    setting_mode = True
+
+            # skipping mode
+            if !setting_mode:
+                # skip any more 1s
+                if regs[rs1] & bit == 1:
+                    i += 1
+                    continue
+
+            # setting mode, search for 1
+            regs[rd] |= bit # always set during search
+            if regs[rs1] & bit: # found a bit in rs1:
+                setting_mode = False
+                # next loop starts skipping
+
+            i += 1
+
+
 ## vmsof
 
 The vector mask set-only-first instruction is similar to set-before-first, except it only sets the first element with a bit set, if any.
 
     sofm RT, RA, RB
 
- # Example
+Example
 
      7 6 5 4 3 2 1 0   Bit number
 
@@ -148,3 +200,32 @@ The vector mask set-only-first instruction is similar to set-before-first, excep
                        vmsof.m v2, v3, v0.t
      0 1 x x x x 0 0   v2 content
 
+Pseudo-code:
+
+    def sof(rd, rs1, rs2):
+        rd = 0
+        setting_mode = rs2 == x0 or (regs[rs2] & 1)
+
+        while i < XLEN:
+            bit = 1<<i
+
+            # only reenable when predicate in use, and bit valid
+            if !setting_mode && rs2 != x0:
+                if (regs[rs2] & bit):
+                    # back into "setting" mode
+                    setting_mode = True
+
+            # skipping mode
+            if !setting_mode:
+                # skip any more 1s
+                if regs[rs1] & bit == 1:
+                    i += 1
+                    continue
+
+            # setting mode, search for 1
+            if regs[rs1] & bit: # found a bit in rs1:
+                regs[rd] |= bit # only set when search succeeds
+                setting_mode = False
+                # next loop starts skipping
+
+            i += 1