* arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b8eea112a86db9dff3626a37ea6d9d194ee0c22b..5e5a7520fd302d44dab6722f33f901d693dbb80f 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2006-07-05  Julian Brown  <julian@codesourcery.com>
+
+       * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
+
 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 977fcf11dbd52ee4aa75710945d89d0ec0b65aa7..a37557889b6f75e5314392c221aef7ac2907974b 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -280,7 +280,7 @@ static const struct opcode32 coprocessor_opcodes[] =
   {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"},
   {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%16-19,0-3d"},
   {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%16-19,0-3d"},
-  {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %y4"},
+  {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"},
   {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"},
   {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"},
   {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"},