fix wrong shift in fmvis, use correct immediates in test

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index f2361333dfecc6b52c129fd1050684cdad7f9dc6..a285d1a317f43d8aad5d3abc703fb12094569102 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -344,12 +344,12 @@ def fmvis(fields):
     # first split imm into d1, d0 and d2. sigh
     d2 = (imm & 1) # LSB (0)
     d1 = (imm >> 1) & 0b11111 # bits 1-5
-    d0 = (imm >> 6) # MSBs 6-15
+    d0 = (imm >> 5) # MSBs 6-15
     return instruction(
         (PO , 0 , 5),
         (FRS, 6 , 10),
-        (d1, 11, 15),
-        (d0, 16, 26),
+        (d1,  11, 15),
+        (d0,  16, 26),
         (XO , 27, 30),
         (d2 , 31, 31),
     )

diff --git a/src/openpower/test/alu/fmvis_cases.py b/src/openpower/test/alu/fmvis_cases.py
index 7562cd1e64f49ce0802a53858d6ee1538cf81790..e698ed36a4d3e58f9e402d301cda669196912369 100644 (file)
--- a/src/openpower/test/alu/fmvis_cases.py
+++ b/src/openpower/test/alu/fmvis_cases.py
@@ -14,14 +14,14 @@ class FMVISTestCase(TestAccumulatorBase):
 
     def case_0_fmvis(self):
         lst = SVP64Asm(["fmvis 5, 0x4000", # 2.0
-                        "fmvis 6, 0x2122",
+                        "fmvis 6, 0x4048", # 3.125
                         "fmvis 7, 0x3E80", # 0.25
                        ])
         lst = list(lst)
 
-        expected_fprs = [0] * 64
+        expected_fprs = [0] * 32 
         expected_fprs[5] = 0x4000000000000000 # 2.0 in FP64 form
-        expected_fprs[6] = 0x2122000000000000
+        expected_fprs[6] = 0x4009000000000000 # 3.125 in FP64 form
         expected_fprs[7] = 0x3FD0000000000000 # 0.25 in FP64 form
         e = ExpectedState(pc=0xc, # 3 instructions so 3x4=0xc
                           fp_regs=expected_fprs) # expected results