from migen.fhdl.std import *
from misoclib.com.liteusb.common import *
-from misoclib.tools.litescope.bridge.wishbone import LiteScopeWishboneBridge
+from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
class LiteUSBWishboneBridge(LiteScopeWishboneBridge):
def __init__(self, port, clk_freq):
"write": 0x01,
"read": 0x02
}
- def __init__(self, interface, mode, tag, addrmap=None, debug=False):
+ def __init__(self, interface, mode, tag, addrmap=None, busword=8, debug=False):
self.interface = interface
self.mode = mode
self.tag = tag
OBJCOPY_quiet = @echo " OBJCOPY " $@ && $(TARGET_PREFIX)objcopy
RANLIB_quiet = @echo " RANLIB " $@ && $(TARGET_PREFIX)ranlib
-MSC_GIT_ID := $(shell cd $(MSCDIR) && python3 -c "from misoclib.cpu.peripherals.identifier.git import get_id; print(hex(get_id()), end='')")
+MSC_GIT_ID := $(shell cd $(MSCDIR) && python3 -c "from misoclib.cpu.git import get_id; print(hex(get_id()), end='')")
ifeq ($(V),1)
CC = $(CC_normal)