(no commit message)

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 747d2dbca0596e0fa5b37dd0238b2aaf09b9d62e..e104522dab60c2dbbec628d2a11b380fd3aa4658 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -47,14 +47,14 @@ The Mode table for Arithmetic and Logical operations,
 being bits 19-23 of SVP64 `RM`, is laid out as
 follows:
 
-| 0-1    |  2  |  3   4  |  description              |
-| ------ | --- |---------|-------------------------- |
+| 0-1    |  2  |  3   4  |  description                     |
+| ------ | --- |---------|----------------------------------|
 | 0   0  |   0 |  dz  sz | simple mode                      |
-| 0   0  |   1 |  RG  0  | scalar reduce mode (mapreduce) |
-| 0   0  |   1 |  /   1  | reserved     |
-| 1   0  |   N | dz   sz |  sat mode: N=0/1 u/s |
+| 0   0  |   1 |  RG  0  | scalar reduce mode (mapreduce)   |
+| 0   0  |   1 |  /   1  | reserved                         |
+| 1   0  |   N | dz   sz |  sat mode: N=0/1 u/s             |
 | VLi 1  | inv | CR-bit  | Rc=1: ffirst CR sel              |
-| VLi 1  | inv | zz RC1  | Rc=0: ffirst z/nonz |
+| VLi 1  | inv | zz RC1  | Rc=0: ffirst z/nonz              |
 
 Fields: