s6ddrphy: fix DFI interface data width computation

diff --git a/misoclib/sdramphy/s6ddrphy.py b/misoclib/sdramphy/s6ddrphy.py
index bdd9d6be041812f40e3db0fbf3a02cceb69d425c..d4f9aa2f332f1e04e913ed1f7f28706aa39e2ced 100644 (file)
--- a/misoclib/sdramphy/s6ddrphy.py
+++ b/misoclib/sdramphy/s6ddrphy.py
@@ -42,7 +42,7 @@ class S6DDRPHY(Module):
                        write_latency=0
                )
 
-               self.dfi = Interface(a, ba, nphases*d, nphases)
+               self.dfi = Interface(a, ba, self.phy_settings.dfi_d, nphases)
                self.clk4x_wr_strb = Signal()
                self.clk4x_rd_strb = Signal()