score.h (IRA_COVER_CLASSES): Define.

2008-12-01  Chen Liqin  <liqin.chen@sunplusct.com>

	* config/score/score.h (IRA_COVER_CLASSES): Define.

From-SVN: r142307

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5602b5a74d9b0c4201c670d3c19c156c06a4b426..feb2d26d79bae2b56d9a47089f61fac3002362e3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2008-12-01  Chen Liqin  <liqin.chen@sunplusct.com>
+
+       * config/score/score.h (IRA_COVER_CLASSES): Define.
+
 2008-11-30  Eric Botcazou  <ebotcazou@adacore.com>
 
        PR target/38287

diff --git a/gcc/config/score/score.h b/gcc/config/score/score.h
index d9900a50214b234658ff8a5c66e21b8b925eb6f1..7f09feb389481fdabba39c4155edd163a285adb7 100644 (file)
--- a/gcc/config/score/score.h
+++ b/gcc/config/score/score.h
@@ -438,6 +438,18 @@ enum reg_class
    also contains the register.  */
 #define REGNO_REG_CLASS(REGNO)         score_reg_class (REGNO)
 
+/* The following macro defines cover classes for Integrated Register
+   Allocator.  Cover classes is a set of non-intersected register
+   classes covering all hard registers used for register allocation
+   purpose.  Any move between two registers of a cover class should be
+   cheaper than load or store of the registers.  The macro value is
+   array of register classes with LIM_REG_CLASSES used as the end
+   marker.  */
+#define IRA_COVER_CLASSES                                      \
+{                                                              \
+  G32_REGS, CE_REGS, SP_REGS, LIM_REG_CLASSES                  \
+}
+
 /* A macro whose definition is the name of the class to which a
    valid base register must belong.  A base register is one used in
    an address which is the register value plus a displacement.  */