re PR target/81616 (Update -mtune=generic for the current Intel and AMD processors)

	PR target/81616
	* x86-tune-costs.h (generic_cost): Reduce cost of FDIV 20->17,
	cost of sqrt 20->14, DIVSS 18->13, DIVSD 32->17, SQRtSS 30->14
	and SQRTsD 58->18, cond_not_taken_branch_cost. 2->1. Increase
	cond_taken_branch_cost 3->4.

From-SVN: r256070

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 97c7a1084d3c87cee3b88e56163141de3f2d0436..57e31cb85eef7fed370ac21ec05c6187546d03ee 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2018-01-02  Jan Hubicka  <hubicka@ucw.cz>
+
+       PR target/81616
+       * x86-tune-costs.h (generic_cost): Reduce cost of FDIV 20->17,
+       cost of sqrt 20->14, DIVSS 18->13, DIVSD 32->17, SQRtSS 30->14
+       and SQRTsD 58->18, cond_not_taken_branch_cost. 2->1. Increase
+       cond_taken_branch_cost 3->4.
+
 2018-01-01  Jakub Jelinek  <jakub@redhat.com>
 
        PR tree-optimization/83581

diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h
index 477e478f1f7769e92fa5325d5a4d4dde79ac9f42..eff7f7f6bbfc2e32e6905108d97a847291cf6c0b 100644 (file)
--- a/gcc/config/i386/x86-tune-costs.h
+++ b/gcc/config/i386/x86-tune-costs.h
@@ -2293,10 +2293,10 @@ struct processor_costs generic_cost = {
   3,                                   /* Branch cost */
   COSTS_N_INSNS (3),                   /* cost of FADD and FSUB insns.  */
   COSTS_N_INSNS (5),                   /* cost of FMUL instruction.  */
-  COSTS_N_INSNS (20),                  /* cost of FDIV instruction.  */
+  COSTS_N_INSNS (17),                  /* cost of FDIV instruction.  */
   COSTS_N_INSNS (1),                   /* cost of FABS instruction.  */
   COSTS_N_INSNS (1),                   /* cost of FCHS instruction.  */
-  COSTS_N_INSNS (20),                  /* cost of FSQRT instruction.  */
+  COSTS_N_INSNS (14),                  /* cost of FSQRT instruction.  */
 
   COSTS_N_INSNS (1),                   /* cost of cheap SSE instruction.  */
   COSTS_N_INSNS (3),                   /* cost of ADDSS/SD SUBSS/SD insns.  */
@@ -2304,15 +2304,15 @@ struct processor_costs generic_cost = {
   COSTS_N_INSNS (5),                   /* cost of MULSD instruction.  */
   COSTS_N_INSNS (5),                   /* cost of FMA SS instruction.  */
   COSTS_N_INSNS (5),                   /* cost of FMA SD instruction.  */
-  COSTS_N_INSNS (18),                  /* cost of DIVSS instruction.  */
-  COSTS_N_INSNS (32),                  /* cost of DIVSD instruction.  */
-  COSTS_N_INSNS (30),                  /* cost of SQRTSS instruction.  */
-  COSTS_N_INSNS (58),                  /* cost of SQRTSD instruction.  */
+  COSTS_N_INSNS (13),                  /* cost of DIVSS instruction.  */
+  COSTS_N_INSNS (17),                  /* cost of DIVSD instruction.  */
+  COSTS_N_INSNS (14),                  /* cost of SQRTSS instruction.  */
+  COSTS_N_INSNS (18),                  /* cost of SQRTSD instruction.  */
   1, 4, 3, 3,                          /* reassoc int, fp, vec_int, vec_fp.  */
   generic_memcpy,
   generic_memset,
-  COSTS_N_INSNS (3),                   /* cond_taken_branch_cost.  */
-  COSTS_N_INSNS (1),                   /* cond_not_taken_branch_cost.  */
+  COSTS_N_INSNS (4),                   /* cond_taken_branch_cost.  */
+  COSTS_N_INSNS (2),                   /* cond_not_taken_branch_cost.  */
 };
 
 /* core_cost should produce code tuned for Core familly of CPUs.  */