intel/compiler: detect if atomic load store operations are used

Patch adds a new arg and modifies existing calls from i965, anv
pass NULL but iris stores this information for later use.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4080>

diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h
index 7a16b46f52d680aa86807245da5dd17691f84d16..0963601d1470d3db125b224cf2ad3990403e2715 100644 (file)
--- a/src/gallium/drivers/iris/iris_context.h
+++ b/src/gallium/drivers/iris/iris_context.h
@@ -361,6 +361,9 @@ struct iris_uncompiled_shader {
 
    bool needs_edge_flag;
 
+   /* Whether shader uses atomic operations. */
+   bool uses_atomic_load_store;
+
    /** Constant data scraped from the shader by nir_opt_large_constants */
    struct pipe_resource *const_data;
 

diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c
index d7e470b4238cd5c85b35d836b4a20cf4b3d626b0..de335cd9803be2c0b745ab4011fae3a6f9a0e7b8 100644 (file)
--- a/src/gallium/drivers/iris/iris_program.c
+++ b/src/gallium/drivers/iris/iris_program.c
@@ -2131,7 +2131,8 @@ iris_create_uncompiled_shader(struct pipe_context *ctx,
 
    brw_preprocess_nir(screen->compiler, nir, NULL);
 
-   NIR_PASS_V(nir, brw_nir_lower_image_load_store, devinfo);
+   NIR_PASS_V(nir, brw_nir_lower_image_load_store, devinfo,
+              &ish->uses_atomic_load_store);
    NIR_PASS_V(nir, iris_lower_storage_image_derefs);
 
    nir_sweep(nir);

diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index 517afe96788c0617966d430f1c4cf08ed1e003da..181f7e5f67c577f9dd9510e77010e18f24d0b5c4 100644 (file)
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -679,6 +679,9 @@ struct brw_stage_prog_data {
     */
    uint32_t *param;
    uint32_t *pull_param;
+
+   /* Whether shader uses atomic operations. */
+   bool uses_atomic_load_store;
 };
 
 static inline uint32_t *

diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h
index 32a8badaa244551e230e72885de7bf484283e4a4..b0ef195c2616b029b903b7d9b52865aec75c6794 100644 (file)
--- a/src/intel/compiler/brw_nir.h
+++ b/src/intel/compiler/brw_nir.h
@@ -121,7 +121,8 @@ void brw_nir_lower_fs_outputs(nir_shader *nir);
 bool brw_nir_lower_conversions(nir_shader *nir);
 
 bool brw_nir_lower_image_load_store(nir_shader *nir,
-                                    const struct gen_device_info *devinfo);
+                                    const struct gen_device_info *devinfo,
+                                    bool *uses_atomic_load_store);
 void brw_nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin,
                                      nir_ssa_def *index);
 void brw_nir_rewrite_bindless_image_intrinsic(nir_intrinsic_instr *intrin,

diff --git a/src/intel/compiler/brw_nir_lower_image_load_store.c b/src/intel/compiler/brw_nir_lower_image_load_store.c
index 3638ed52ec51bc62ef594da2d4d13d00fabfbd4f..88b756b0775feebf7b0b2c8bd3fcc3b9e831d979 100644 (file)
--- a/src/intel/compiler/brw_nir_lower_image_load_store.c
+++ b/src/intel/compiler/brw_nir_lower_image_load_store.c
@@ -680,7 +680,8 @@ lower_image_size_instr(nir_builder *b,
 
 bool
 brw_nir_lower_image_load_store(nir_shader *shader,
-                               const struct gen_device_info *devinfo)
+                               const struct gen_device_info *devinfo,
+                               bool *uses_atomic_load_store)
 {
    bool progress = false;
 
@@ -718,6 +719,8 @@ brw_nir_lower_image_load_store(nir_shader *shader,
             case nir_intrinsic_image_deref_atomic_xor:
             case nir_intrinsic_image_deref_atomic_exchange:
             case nir_intrinsic_image_deref_atomic_comp_swap:
+               if (uses_atomic_load_store)
+                  *uses_atomic_load_store = true;
                if (lower_image_atomic_instr(&b, devinfo, intrin))
                   progress = true;
                break;

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 15fc5c2df52013d0cd8f3f852b304859506bc1cb..12dcb024acb2ab05852b0883900d5b504f51e80a 100644 (file)
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -692,7 +692,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
 
    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 
-   NIR_PASS_V(nir, brw_nir_lower_image_load_store, compiler->devinfo);
+   NIR_PASS_V(nir, brw_nir_lower_image_load_store, compiler->devinfo, NULL);
 
    NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_global,
               nir_address_format_64bit_global);

diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 9933eb27e7e1f6c4473caf19db966f59886de010..d250f02825b7baf59d2cd5af15cad3ee3618bd5e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -186,7 +186,7 @@ brw_nir_lower_resources(nir_shader *nir, struct gl_shader_program *shader_prog,
    prog->info.textures_used = prog->nir->info.textures_used;
    prog->info.textures_used_by_txf = prog->nir->info.textures_used_by_txf;
 
-   NIR_PASS_V(prog->nir, brw_nir_lower_image_load_store, devinfo);
+   NIR_PASS_V(prog->nir, brw_nir_lower_image_load_store, devinfo, NULL);
 
    if (prog->nir->info.stage == MESA_SHADER_COMPUTE &&
        shader_prog->data->spirv) {