+2015-10-21 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
+
+ * cfgrtl.c (pass_free_cfg::execute): Adjust.
+ * final.c (dbr_sequence_length): Always define.
+ (shorten_branches): Adjust.
+ * genattr-common.c (main): Always define DELAY_SLOTS.
+ * genattr.c (main): Unconditionally declare functions and define
+ macros related to delay slots.
+ * genattrtab.c (write_eligible_delay): Adjust.
+ (main): Always write out delay slot functions.
+ * opts.c (default_options_table): Adjust.
+ * reorg.c (redirect_with_delay_slots_safe_p): Likewise.
+ (redirect_with_delay_list_safe_p): Likewise.
+ (fill_simple_delay_slots): Likewise.
+ (fill_slots_from_thread): Likewise.
+ (make_return_insns): Likewise.
+ (dbr_schedule): Likewise.
+ (rest_of_handle_delay_slots): Likewise.
+ (pass_delay_slots::gate): Likewise.
+ * toplev.c (process_options): Likewise.
+
2015-10-21 Richard Henderson <rth@redhat.com>
* targhooks.c (default_addr_space_pointer_mode): Remove check
unsigned int
pass_free_cfg::execute (function *)
{
-#ifdef DELAY_SLOTS
/* The resource.c machinery uses DF but the CFG isn't guaranteed to be
valid at that point so it would be too late to call df_analyze. */
- if (optimize > 0 && flag_delayed_branch)
+ if (DELAY_SLOTS && optimize > 0 && flag_delayed_branch)
{
df_note_add_problem ();
df_analyze ();
}
-#endif
if (crtl->has_bb_partition)
insert_section_boundary_note ();
delayed branch sequence (we don't count the insn needing the
delay slot). Zero if not in a delayed branch sequence. */
-#ifdef DELAY_SLOTS
int
dbr_sequence_length (void)
{
else
return 0;
}
-#endif
\f
/* The next two pages contain routines used to compute the length of an insn
and to shorten branches. */
{
int i;
int const_delay_slots;
-#ifdef DELAY_SLOTS
- const_delay_slots = const_num_delay_slots (body_seq->insn (0));
-#else
- const_delay_slots = 0;
-#endif
+ if (DELAY_SLOTS)
+ const_delay_slots = const_num_delay_slots (body_seq->insn (0));
+ else
+ const_delay_slots = 0;
+
int (*inner_length_fun) (rtx_insn *)
= const_delay_slots ? length_fun : insn_default_length;
/* Inside a delay slot sequence, we do not do any branch shortening
break;
case DEFINE_DELAY:
- if (!have_delay)
- {
- printf ("#define DELAY_SLOTS\n");
- have_delay = true;
- }
+ have_delay = true;
break;
case DEFINE_INSN_RESERVATION:
default:
break;
}
+
+ printf ("#define DELAY_SLOTS %d\n", have_delay);
puts ("\n#endif /* GCC_INSN_ATTR_COMMON_H */");
if (ferror (stdout) || fflush (stdout) || fclose (stdout))
int
main (int argc, char **argv)
{
- int have_delay = 0;
- int have_annul_true = 0;
- int have_annul_false = 0;
+ bool have_annul_true = false;
+ bool have_annul_false = false;
int num_insn_reservations = 0;
int i;
break;
case DEFINE_DELAY:
- if (! have_delay)
- {
- printf ("extern int num_delay_slots (rtx_insn *);\n");
- printf ("extern int eligible_for_delay (rtx_insn *, int, rtx_insn *, int);\n\n");
- printf ("extern int const_num_delay_slots (rtx_insn *);\n\n");
- have_delay = 1;
- }
-
for (i = 0; i < XVECLEN (def, 1); i += 3)
{
- if (XVECEXP (def, 1, i + 1) && ! have_annul_true)
- {
- printf ("#define ANNUL_IFTRUE_SLOTS\n");
- printf ("extern int eligible_for_annul_true (rtx_insn *, int, rtx_insn *, int);\n");
- have_annul_true = 1;
- }
-
- if (XVECEXP (def, 1, i + 2) && ! have_annul_false)
- {
- printf ("#define ANNUL_IFFALSE_SLOTS\n");
- printf ("extern int eligible_for_annul_false (rtx_insn *, int, rtx_insn *, int);\n");
- have_annul_false = 1;
- }
+ if (XVECEXP (def, 1, i + 1))
+ have_annul_true = true;
+
+ if (XVECEXP (def, 1, i + 2))
+ have_annul_false = true;
}
break;
}
}
+ printf ("extern int num_delay_slots (rtx_insn *);\n");
+ printf ("extern int eligible_for_delay (rtx_insn *, int, rtx_insn *, int);\n\n");
+ printf ("extern int const_num_delay_slots (rtx_insn *);\n\n");
+ printf ("#define ANNUL_IFTRUE_SLOTS %d\n", have_annul_true);
+ printf ("extern int eligible_for_annul_true (rtx_insn *, int, rtx_insn *, int);\n");
+ printf ("#define ANNUL_IFFALSE_SLOTS %d\n", have_annul_false);
+ printf ("extern int eligible_for_annul_false (rtx_insn *, int, rtx_insn *, int);\n");
+
if (num_insn_reservations > 0)
{
bool has_tune_attr
" rtx_insn *candidate_insn, int flags ATTRIBUTE_UNUSED)\n",
kind);
fprintf (outf, "{\n");
- fprintf (outf, " rtx_insn *insn;\n");
+ fprintf (outf, " rtx_insn *insn ATTRIBUTE_UNUSED;\n");
fprintf (outf, "\n");
fprintf (outf, " gcc_assert (slot < %d);\n", max_slots);
fprintf (outf, "\n");
}
/* Expand DEFINE_DELAY information into new attribute. */
- if (num_delays)
- expand_delays ();
+ expand_delays ();
/* Make `insn_alternatives'. */
int num_insn_codes = get_num_insn_codes ();
/* Write out delay eligibility information, if DEFINE_DELAY present.
(The function to compute the number of delay slots will be written
below.) */
- if (num_delays)
- {
- write_eligible_delay (attr_file, "delay");
- if (have_annul_true)
- write_eligible_delay (attr_file, "annul_true");
- if (have_annul_false)
- write_eligible_delay (attr_file, "annul_false");
- }
+ write_eligible_delay (attr_file, "delay");
+ write_eligible_delay (attr_file, "annul_true");
+ write_eligible_delay (attr_file, "annul_false");
/* Write out constant delay slot info. */
write_const_num_delay_slots (attr_file);
{
/* -O1 optimizations. */
{ OPT_LEVELS_1_PLUS, OPT_fdefer_pop, NULL, 1 },
-#ifdef DELAY_SLOTS
+#if DELAY_SLOTS
{ OPT_LEVELS_1_PLUS, OPT_fdelayed_branch, NULL, 1 },
#endif
{ OPT_LEVELS_1_PLUS, OPT_fguess_branch_probability, NULL, 1 },
#include "target.h"
#include "tree-pass.h"
-#ifdef DELAY_SLOTS
-
-#ifndef ANNUL_IFTRUE_SLOTS
-#define eligible_for_annul_true(INSN, SLOTS, TRIAL, FLAGS) 0
-#endif
-#ifndef ANNUL_IFFALSE_SLOTS
-#define eligible_for_annul_false(INSN, SLOTS, TRIAL, FLAGS) 0
-#endif
-
\f
/* First, some functions that were used before GCC got a control flow graph.
These functions are now only used here in reorg.c, and have therefore
static rtx_insn *delete_from_delay_slot (rtx_insn *);
static void delete_scheduled_jump (rtx_insn *);
static void note_delay_statistics (int, int);
-#if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
-static void optimize_skip (rtx_jump_insn *, vec<rtx_insn *> *);
-#endif
static int get_jump_flags (const rtx_insn *, rtx);
static int mostly_true_jump (rtx);
static rtx get_branch_condition (const rtx_insn *, rtx);
num_filled_delays[index][slots_filled][reorg_pass_number]++;
}
\f
-#if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
-
/* Optimize the following cases:
1. When a conditional branch skips over only one instruction,
INSN_ANNULLED_BRANCH_P (insn) = 1;
}
}
-#endif
\f
/* Encode and return branch direction and prediction information for
INSN assuming it will jump to LABEL.
flags = get_jump_flags (jump, newlabel);
for (i = 1; i < pat->len (); i++)
if (! (
-#ifdef ANNUL_IFFALSE_SLOTS
+#if ANNUL_IFFALSE_SLOTS
(INSN_ANNULLED_BRANCH_P (jump)
&& INSN_FROM_TARGET_P (pat->insn (i)))
? eligible_for_annul_false (jump, i - 1, pat->insn (i), flags) :
#endif
-#ifdef ANNUL_IFTRUE_SLOTS
+#if ANNUL_IFTRUE_SLOTS
(INSN_ANNULLED_BRANCH_P (jump)
&& ! INSN_FROM_TARGET_P (XVECEXP (pat, 0, i)))
? eligible_for_annul_true (jump, i - 1, pat->insn (i), flags) :
unsigned int i = 0;
for (; i < delay_insns; i++)
if (! (
-#ifdef ANNUL_IFFALSE_SLOTS
+#if ANNUL_IFFALSE_SLOTS
(INSN_ANNULLED_BRANCH_P (jump)
&& INSN_FROM_TARGET_P (delay_list[i]))
? eligible_for_annul_false (jump, i, delay_list[i], flags) :
#endif
-#ifdef ANNUL_IFTRUE_SLOTS
+#if ANNUL_IFTRUE_SLOTS
(INSN_ANNULLED_BRANCH_P (jump)
&& ! INSN_FROM_TARGET_P (delay_list[i]))
? eligible_for_annul_true (jump, i, delay_list[i], flags) :
/* If all needed slots haven't been filled, we come here. */
/* Try to optimize case of jumping around a single insn. */
-#if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
- if (slots_filled != slots_to_fill
+ if ((ANNUL_IFTRUE_SLOTS || ANNUL_IFFALSE_SLOTS)
+ && slots_filled != slots_to_fill
&& delay_list.is_empty ()
&& JUMP_P (insn)
&& (condjump_p (insn) || condjump_in_parallel_p (insn))
if (!delay_list.is_empty ())
slots_filled += 1;
}
-#endif
/* Try to get insns from beyond the insn needing the delay slot.
These insns can neither set or reference resources set in insns being
goto winner;
}
else if (0
-#ifdef ANNUL_IFTRUE_SLOTS
- || ! thread_if_true
-#endif
-#ifdef ANNUL_IFFALSE_SLOTS
- || thread_if_true
-#endif
- )
+ || (ANNUL_IFTRUE_SLOTS && ! thread_if_true)
+ || (ANNUL_IFFALSE_SLOTS && thread_if_true))
{
old_trial = trial;
trial = try_split (pat, trial, 0);
{
for (i = 1; i < XVECLEN (pat, 0); i++)
if (! (
-#ifdef ANNUL_IFFALSE_SLOTS
+#if ANNUL_IFFALSE_SLOTS
(INSN_ANNULLED_BRANCH_P (jump_insn)
&& INSN_FROM_TARGET_P (pat->insn (i)))
? eligible_for_annul_false (jump_insn, i - 1,
pat->insn (i), flags) :
#endif
-#ifdef ANNUL_IFTRUE_SLOTS
+#if ANNUL_IFTRUE_SLOTS
(INSN_ANNULLED_BRANCH_P (jump_insn)
&& ! INSN_FROM_TARGET_P (pat->insn (i)))
? eligible_for_annul_true (jump_insn, i - 1,
}
}
fprintf (dump_file, "\n");
-#if defined (ANNUL_IFTRUE_SLOTS) || defined (ANNUL_IFFALSE_SLOTS)
- fprintf (dump_file, ";; Reorg annuls: ");
- need_comma = 0;
- for (j = 0; j < MAX_DELAY_HISTOGRAM + 1; j++)
+
+ if (ANNUL_IFTRUE_SLOTS || ANNUL_IFFALSE_SLOTS)
{
- if (total_annul_slots[j])
+ fprintf (dump_file, ";; Reorg annuls: ");
+ need_comma = 0;
+ for (j = 0; j < MAX_DELAY_HISTOGRAM + 1; j++)
{
- if (need_comma)
- fprintf (dump_file, ", ");
- need_comma = 1;
- fprintf (dump_file, "%d got %d delays", total_annul_slots[j], j);
+ if (total_annul_slots[j])
+ {
+ if (need_comma)
+ fprintf (dump_file, ", ");
+ need_comma = 1;
+ fprintf (dump_file, "%d got %d delays", total_annul_slots[j], j);
+ }
}
+ fprintf (dump_file, "\n");
}
- fprintf (dump_file, "\n");
-#endif
+
fprintf (dump_file, "\n");
}
free (uid_to_ruid);
crtl->dbr_scheduled_p = true;
}
-#endif /* DELAY_SLOTS */
\f
/* Run delay slot optimization. */
static unsigned int
rest_of_handle_delay_slots (void)
{
-#ifdef DELAY_SLOTS
- dbr_schedule (get_insns ());
-#endif
+ if (DELAY_SLOTS)
+ dbr_schedule (get_insns ());
+
return 0;
}
bool
pass_delay_slots::gate (function *)
{
-#ifdef DELAY_SLOTS
/* At -O0 dataflow info isn't updated after RA. */
- return optimize > 0 && flag_delayed_branch && !crtl->dbr_scheduled_p;
-#else
- return 0;
-#endif
+ if (DELAY_SLOTS)
+ return optimize > 0 && flag_delayed_branch && !crtl->dbr_scheduled_p;
+
+ return false;
}
} // anon namespace
if (flag_schedule_insns || flag_schedule_insns_after_reload)
warning (0, "instruction scheduling not supported on this target machine");
#endif
-#ifndef DELAY_SLOTS
- if (flag_delayed_branch)
+ if (!DELAY_SLOTS && flag_delayed_branch)
warning (0, "this target machine does not have delayed branches");
-#endif
user_label_prefix = USER_LABEL_PREFIX;
if (flag_leading_underscore != -1)