rename expected to results (actual results)

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index 5e015016be7f5d56e5202baf212dee71b8023e52..df6873c8681f522de75948b3b326021b77700c51 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -85,11 +85,11 @@ class DecoderTestCase(FHDLTestCase):
             print("spr svshape1", sim.spr['SVSHAPE1'])
             print("spr svshape2", sim.spr['SVSHAPE2'])
             print("spr svshape3", sim.spr['SVSHAPE3'])
-            expected = []
+            results = []
             for i in range(4):
-                expected.append(sim.gpr(i).asint())
+                results.append(sim.gpr(i).asint())
             for i in range(4):
-                print("maddld-matrix i", i, expected[i])
+                print("maddld-matrix i", i, results[i])
             # confirm that the results are as expected
             # for i, (t, u) in enumerate(res):
             #    self.assertEqual(sim.fpr(i+2), t)