r300_emit_vertex_program_code(r300, &r300_passthrough_vertex_shader, 0);
} else {
BEGIN_CS(4);
- OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VAP_TCL_BYPASS);
+ OUT_CS_REG(R300_VAP_CNTL_STATUS,
+#ifdef PIPE_ARCH_BIG_ENDIAN
+ R300_VC_32BIT_SWAP |
+#endif
+ R300_VAP_TCL_BYPASS);
OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(5) |
R300_PVS_NUM_CNTLRS(5) |
R300_PVS_NUM_FPUS(caps->num_vert_fpus) |
r300_emit_vertex_program_code(r300, &r300_passthrough_vertex_shader, 0);
} else {
BEGIN_CS(4);
- OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VAP_TCL_BYPASS);
+ OUT_CS_REG(R300_VAP_CNTL_STATUS,
+#ifdef PIPE_ARCH_BIG_ENDIAN
+ R300_VC_32BIT_SWAP |
+#endif
+ R300_VAP_TCL_BYPASS);
OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(5) |
R300_PVS_NUM_CNTLRS(5) |
R300_PVS_NUM_FPUS(caps->num_vert_fpus) |