panfrost: Add an helper to update the rasterizer part of a tiler job desc
authorBoris Brezillon <boris.brezillon@collabora.com>
Thu, 5 Mar 2020 10:52:12 +0000 (11:52 +0100)
committerBoris Brezillon <boris.brezillon@collabora.com>
Tue, 10 Mar 2020 11:47:34 +0000 (12:47 +0100)
That's part of our attempt to make panfrost_emit_for_draw() a bit more
dry and eventually get rid of it by inlining the code in
panfrost_draw_vbo(). This is just one step in this direction.

Note that we get rid of the panfrost_rasterizer.tiler_gl_enables field
along the way, as setting/clearing those bits at draw time instead of
doing when the state is created should make a huge difference. We might
get back to pre-computed VT descs at some point, but let's keep things
simple for now.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4083>

src/gallium/drivers/panfrost/pan_cmdstream.c
src/gallium/drivers/panfrost/pan_cmdstream.h
src/gallium/drivers/panfrost/pan_context.c
src/gallium/drivers/panfrost/pan_context.h

index d1f8c754182bc94f838a960ca8e570967a9c2aef..b6b569ceb5f56f04bf7ca03e749641bf43a3f81f 100644 (file)
@@ -59,6 +59,35 @@ panfrost_vt_attach_framebuffer(struct panfrost_context *ctx,
         vt->postfix.shared_memory = batch->framebuffer.gpu;
 }
 
+void
+panfrost_vt_update_rasterizer(struct panfrost_context *ctx,
+                              struct midgard_payload_vertex_tiler *tp)
+{
+        struct panfrost_rasterizer *rasterizer = ctx->rasterizer;
+
+        tp->gl_enables |= 0x7;
+        SET_BIT(tp->gl_enables, MALI_FRONT_CCW_TOP,
+                rasterizer && rasterizer->base.front_ccw);
+        SET_BIT(tp->gl_enables, MALI_CULL_FACE_FRONT,
+                rasterizer && (rasterizer->base.cull_face & PIPE_FACE_FRONT));
+        SET_BIT(tp->gl_enables, MALI_CULL_FACE_BACK,
+                rasterizer && (rasterizer->base.cull_face & PIPE_FACE_BACK));
+        SET_BIT(tp->prefix.unknown_draw, MALI_DRAW_FLATSHADE_FIRST,
+                rasterizer && rasterizer->base.flatshade_first);
+
+        if (!panfrost_writes_point_size(ctx)) {
+                bool points = tp->prefix.draw_mode == MALI_POINTS;
+                float val = 0.0f;
+
+                if (rasterizer)
+                        val = points ?
+                              rasterizer->base.point_size :
+                              rasterizer->base.line_width;
+
+                tp->primitive_size.constant = val;
+        }
+}
+
 void
 panfrost_vt_update_occlusion_query(struct panfrost_context *ctx,
                                    struct midgard_payload_vertex_tiler *tp)
index 92544d2a37bd3a68d69c3d500dbad08de34c9719..2fa088b369c8e304681bd3f5a6472553eb9fb2b3 100644 (file)
@@ -36,6 +36,10 @@ void
 panfrost_vt_attach_framebuffer(struct panfrost_context *ctx,
                                struct midgard_payload_vertex_tiler *vt);
 
+void
+panfrost_vt_update_rasterizer(struct panfrost_context *ctx,
+                              struct midgard_payload_vertex_tiler *tp);
+
 void
 panfrost_vt_update_occlusion_query(struct panfrost_context *ctx,
                                    struct midgard_payload_vertex_tiler *tp);
index d2cb94037f52be992a06db4e5b6e2cd4be314534..5904645aa250158a474109068367a6c22c9d3df7 100644 (file)
@@ -544,7 +544,6 @@ panfrost_emit_for_draw(struct panfrost_context *ctx)
 
         if (ctx->rasterizer) {
                 bool msaa = ctx->rasterizer->base.multisample;
-                ctx->payloads[PIPE_SHADER_FRAGMENT].gl_enables = ctx->rasterizer->tiler_gl_enables;
 
                 /* TODO: Sample size */
                 SET_BIT(ctx->fragment_shader_core.unknown2_3, MALI_HAS_MSAA, msaa);
@@ -553,27 +552,13 @@ panfrost_emit_for_draw(struct panfrost_context *ctx)
 
         panfrost_batch_set_requirements(batch);
 
+        panfrost_vt_update_rasterizer(ctx, &ctx->payloads[PIPE_SHADER_FRAGMENT]);
         panfrost_vt_update_occlusion_query(ctx, &ctx->payloads[PIPE_SHADER_FRAGMENT]);
 
         panfrost_patch_shader_state(ctx, PIPE_SHADER_VERTEX);
         panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX,
                                   &ctx->payloads[PIPE_SHADER_VERTEX]);
 
-        if (ctx->shader[PIPE_SHADER_VERTEX] && ctx->shader[PIPE_SHADER_FRAGMENT]) {
-                /* Check if we need to link the gl_PointSize varying */
-                if (!panfrost_writes_point_size(ctx)) {
-                        /* If the size is constant, write it out. Otherwise,
-                         * don't touch primitive_size (since we would clobber
-                         * the pointer there) */
-
-                        bool points = ctx->payloads[PIPE_SHADER_FRAGMENT].prefix.draw_mode == MALI_POINTS;
-
-                        ctx->payloads[PIPE_SHADER_FRAGMENT].primitive_size.constant = points ?
-                                ctx->rasterizer->base.point_size :
-                                ctx->rasterizer->base.line_width;
-                }
-        }
-
         if (ctx->shader[PIPE_SHADER_FRAGMENT]) {
                 struct panfrost_shader_state *variant = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
 
@@ -1110,18 +1095,6 @@ panfrost_create_rasterizer_state(
 
         so->base = *cso;
 
-        /* Bitmask, unknown meaning of the start value. 0x105 on 32-bit T6XX */
-        so->tiler_gl_enables = 0x7;
-
-        if (cso->front_ccw)
-                so->tiler_gl_enables |= MALI_FRONT_CCW_TOP;
-
-        if (cso->cull_face & PIPE_FACE_FRONT)
-                so->tiler_gl_enables |= MALI_CULL_FACE_FRONT;
-
-        if (cso->cull_face & PIPE_FACE_BACK)
-                so->tiler_gl_enables |= MALI_CULL_FACE_BACK;
-
         return so;
 }
 
index 768e1cd30df1b0820c297e3a32edb146da7e55b2..b6eb7206b80dff8f17bc04301b31c4629727e929 100644 (file)
@@ -178,9 +178,6 @@ struct panfrost_context {
 
 struct panfrost_rasterizer {
         struct pipe_rasterizer_state base;
-
-        /* Bitmask of front face, etc */
-        unsigned tiler_gl_enables;
 };
 
 /* Variants bundle together to form the backing CSO, bundling multiple