fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis...

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index b4bd534e9458936ada6dd263367149781bff8741..3b5e4cf5dea6c4188978d5cba6aff4efb6498bef 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -276,11 +276,19 @@ def _printinit(f, ios, ns):
                - ios \
                - list_targets(f) \
                - list_special_ios(f, False, True, True)
+       wires = (_list_comb_wires(f) | list_special_ios(f, True, False, False)) \
+               - ios \
+               - list_targets(f) \
+               - list_special_ios(f, False, True, True)
        if signals:
-               r += "initial begin\n"
                for s in sorted(signals, key=lambda x: x.huid):
-                       r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
-               r += "end\n\n"
+                       if s in wires:
+                               r += "assign" + ns.get_name(s) + " = " + _printexpr(ns, s.reset)[0] + ";\n"
+               r += "always @(*) begin\n"
+               for s in sorted(signals, key=lambda x: x.huid):
+                       if s not in wires:
+                               r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
+               r += "end\n"
        return r
 
 def convert(f, ios=None, name="top",