nMigen is *not* a "Python-to-FPGA" conventional high level synthesis
(HLS) tool. It will *not* take a Python program as input and generate a
hardware implementation of it. If you prefer this style of HLS, you may
-wish to try [MyHDL](https://myhdl.org). In nMigen, the Python program is
-executed by a regular Python interpreter, and it emits explicit statements
-in the FHDL domain-specific language. Writing a conventional HLS tool,
+wish to try [MyHDL](https://myhdl.org). In nMigen, the Python program
+is executed by a regular Python interpreter, and it emits explicit
+statements in the FHDL domain-specific language. Therefore, unlike MyHDL
+(which is restricted to a subset of python), it is possible to use the
+full OO power of python to create HDL. Writing a conventional HLS tool,
similar to MyHDL, that uses nMigen as an internal component might be a
good idea, on the other hand :)