gallium/radeon: add helpers for whether HTILE is enabled

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 764acfcad75d85cadef5abb341601ac57d2e4dda..a9b503f9f10b1847540443cf68e10617468274ee 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1392,8 +1392,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
                                        S_028044_FORMAT(V_028044_STENCIL_8);
        }
 
-       /* use htile only for first level */
-       if (rtex->htile_offset && !level) {
+       if (r600_htile_enabled(rtex, level)) {
                uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
                surf->db_htile_data_base = va >> 8;
                surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) |

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 79505d501d01677624c730fb73efe737db644778..783d8c8a3bcf0589f51e613eca10a82f92846247 100644 (file)
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -443,8 +443,7 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers,
                 * array are clear to different value. To simplify code just
                 * disable fast clear for texture array.
                 */
-               /* Only use htile for first level */
-               if (rtex->htile_offset && !level &&
+               if (r600_htile_enabled(rtex, level) &&
                    fb->zsbuf->u.tex.first_layer == 0 &&
                    fb->zsbuf->u.tex.last_layer == util_max_layer(&rtex->resource.b.b, level)) {
                        if (rtex->depth_clear_value != depth) {

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 300dbe8040c2a20bc15da3fa76ca55eb857b2fd9..c21e8dabb1fd3f123059a08454ad5f202de4bba6 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1060,8 +1060,7 @@ static void r600_init_depth_surface(struct r600_context *rctx,
        surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
        surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1;
 
-       /* use htile only for first level */
-       if (rtex->htile_offset && !level) {
+       if (r600_htile_enabled(rtex, level)) {
                surf->db_htile_data_base = rtex->htile_offset >> 8;
                surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
                                         S_028D24_HTILE_HEIGHT(1) |

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 813ea067f1608907d6c5dea70de08cef4665f163..59886ecccc6335c7ee9647cb51e8c0c78e89b31f 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -1006,6 +1006,19 @@ vi_dcc_enabled(struct r600_texture *tex, unsigned level)
        return tex->dcc_offset && level < tex->surface.num_dcc_levels;
 }
 
+static inline bool
+r600_htile_enabled(struct r600_texture *tex, unsigned level)
+{
+       return tex->htile_offset && level == 0;
+}
+
+static inline bool
+vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
+{
+       assert(!tex->tc_compatible_htile || tex->htile_offset);
+       return tex->tc_compatible_htile && level == 0;
+}
+
 #define COMPUTE_DBG(rscreen, fmt, args...) \
        do { \
                if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 4e3b707b6cfad8587984aba968cfb5c8ae8200e8..8add28f2060024f38f602999031aec0449742fd3 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -381,7 +381,9 @@ si_decompress_depth(struct si_context *sctx,
        }
 
        if (inplace_planes) {
-               if (!tex->tc_compatible_htile) {
+               bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, first_level);
+
+               if (!tc_compat_htile) {
                        si_blit_decompress_zs_in_place(
                                                sctx, tex,
                                                levels_z, levels_s,
@@ -393,10 +395,9 @@ si_decompress_depth(struct si_context *sctx,
                 */
                si_make_DB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
                                           inplace_planes & PIPE_MASK_S,
-                                          tex->tc_compatible_htile &&
-                                          first_level == 0);
+                                          tc_compat_htile);
 
-               if (tex->tc_compatible_htile) {
+               if (tc_compat_htile) {
                        /* Only clear the mask that we are flushing, because
                         * si_make_DB_shader_coherent() can treat depth and
                         * stencil differently.
@@ -859,8 +860,8 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
                }
        }
 
-       if (zstex && zstex->htile_offset &&
-           zsbuf->u.tex.level == 0 &&
+       if (zstex &&
+           r600_htile_enabled(zstex, zsbuf->u.tex.level) &&
            zsbuf->u.tex.first_layer == 0 &&
            zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
                /* TC-compatible HTILE only supports depth clears to 0 or 1. */

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 646a9ec2570fcb7637ad3adef5adf5714b065365..446c52e74782a6c7283e6642edbb7443abd5c645 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -330,7 +330,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
                        }
 
                        meta_va |= (uint32_t)tex->surface.tile_swizzle << 8;
-               } else if (tex->tc_compatible_htile && first_level == 0) {
+               } else if (vi_tc_compat_htile_enabled(tex, first_level)) {
                        meta_va = tex->resource.gpu_address + tex->htile_offset;
                }
 

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index d391d5f501a99138d3259bc176244eb60e292c1c..cdcac0742c7b4df782f41ab1a190c85cf9a6021b 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2327,8 +2327,7 @@ static void si_init_depth_surface(struct si_context *sctx,
                surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
                                      S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
 
-               /* Only use HTILE for the first level. */
-               if (rtex->htile_offset && !level) {
+               if (r600_htile_enabled(rtex, level)) {
                        z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
                                  S_028038_ALLOW_EXPCLEAR(1);
 
@@ -2406,8 +2405,7 @@ static void si_init_depth_surface(struct si_context *sctx,
                surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
                                                                levelinfo->nblk_y) / 64 - 1);
 
-               /* Only use HTILE for the first level. */
-               if (rtex->htile_offset && !level) {
+               if (r600_htile_enabled(rtex, level)) {
                        z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
                                  S_028040_ALLOW_EXPCLEAR(1);
 
@@ -2668,7 +2666,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
                        si_init_depth_surface(sctx, surf);
                }
 
-               if (rtex->tc_compatible_htile && !surf->base.u.tex.level)
+               if (vi_tc_compat_htile_enabled(rtex, surf->base.u.tex.level))
                        sctx->framebuffer.DB_has_shader_readable_metadata = true;
 
                r600_context_add_resource_size(ctx, surf->base.texture);