| ``--stbv`` | Use large bit vectors (instead of uninterpreted |
| | functions) to represent the circuit state. |
+-----------------+---------------------------------------------------------+
+| ``--stdt`` | Use SMT-LIB 2.6 datatypes to represent states. |
++-----------------+---------------------------------------------------------+
| ``--nopresat`` | Do not run "presat" SMT queries that make sure that |
| | assumptions are non-conflicting (and potentially |
| | warmup the SMT solver). |
return [task]
- if re.match(r"^smt2(_syn)?(_nomem)?(_stbv)?$", model_name):
+ if re.match(r"^smt2(_syn)?(_nomem)?(_stbv|_stdt)?$", model_name):
with open("%s/model/design_%s.ys" % (self.workdir, model_name), "w") as f:
print("# running in %s/model/" % (self.workdir), file=f)
print("read_ilang design.il", file=f)
print("stat", file=f)
if "_stbv" in model_name:
print("write_smt2 -stbv -wires design_%s.smt2" % model_name, file=f)
+ elif "_stdt" in model_name:
+ print("write_smt2 -stdt -wires design_%s.smt2" % model_name, file=f)
else:
print("write_smt2 -wires design_%s.smt2" % model_name, file=f)
unroll_opt = None
syn_opt = False
stbv_opt = False
+ stdt_opt = False
dumpsmt2 = False
- opts, args = getopt.getopt(engine[1:], "", ["nomem", "syn", "stbv", "presat", "nopresat", "unroll", "nounroll", "dumpsmt2"])
+ opts, args = getopt.getopt(engine[1:], "", ["nomem", "syn", "stbv", "stdt", "presat", "nopresat", "unroll", "nounroll", "dumpsmt2"])
for o, a in opts:
if o == "--nomem":
syn_opt = True
elif o == "--stbv":
stbv_opt = True
+ elif o == "--stdt":
+ stdt_opt = True
elif o == "--presat":
presat_opt = True
elif o == "--nopresat":
if syn_opt: model_name += "_syn"
if nomem_opt: model_name += "_nomem"
if stbv_opt: model_name += "_stbv"
+ if stdt_opt: model_name += "_stdt"
if mode == "prove":
run("prove_basecase", job, engine_idx, engine)