addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=20
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
sim_ticks 1884235597000 # Number of ticks simulated
final_tick 1884235597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 284222 # Simulator instruction rate (inst/s)
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sim_insts 56122640 # Number of instructions simulated
sim_ops 56122640 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 25915776 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::total 1053184 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::total 7561856 # Number of bytes written to this memory
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system.physmem.num_reads::total 404934 # Number of read requests responded to by this memory
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system.physmem.num_writes::total 118154 # Number of write requests responded to by this memory
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system.physmem.bw_write::total 4013222 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::total 17767222 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 404934 # Number of read requests accepted
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system.cpu.dcache.tags.avg_refs 9.866386 # Average number of references to valid blocks.
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sim_insts 125221621 # Number of instructions simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::total 12926236 # Number of bytes read from this memory
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system.physmem.bw_read::total 4542147 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 3160782 # Write bandwidth from this memory (bytes/s)
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sim_insts 895084962 # Number of instructions simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s)
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
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system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks.
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269 # average ReadReq miss latency
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system.cpu0.dcache.overall_avg_miss_latency::total 15775.222968 # average overall miss latency
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system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5338553005 # number of WriteReq MSHR uncacheable cycles
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system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15010557747 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for ReadReq accesses
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system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.107106 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
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system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.746347 # mshr miss rate for WriteInvalidateReq accesses
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system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.648936 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813285 # mshr miss rate for SCUpgradeReq accesses
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system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231718 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for demand accesses
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system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for overall accesses
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system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
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system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928 # average ReadReq mshr miss latency
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system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406 # average HardPFReq mshr miss latency
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system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561 # average WriteInvalidateReq mshr miss latency
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system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 16482247 # Transaction distribution
system.cpu1.dcache.tags.sampled_refs 5624987 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 28.670368 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8377201144000 # Cycle when the warmup percentage was hit.
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system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 342291215 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 342291215 # Number of data accesses
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system.cpu1.dcache.overall_accesses::total 163642606 # number of overall (read+write) accesses
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system.cpu1.dcache.ReadReq_miss_rate::total 0.049103 # miss rate for ReadReq accesses
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system.cpu1.dcache.WriteReq_miss_rate::total 0.031209 # miss rate for WriteReq accesses
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system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.068952 # miss rate for LoadLockedReq accesses
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system.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044 # average ReadReq miss latency
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system.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856 # average WriteReq miss latency
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-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.467828 # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.775863 # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.467828 # mshr miss rate for WriteInvalidateReq accesses
system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677328 # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.601667 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.583921 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.601667 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.583921 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.592611 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.584394 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.585970 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.584394 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.585970 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.585217 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.576077 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.508392 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.576077 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508392 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.545673 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.290745 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.250730 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.226304 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.181335 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.290745 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.148944 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.250730 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.226304 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67591.919720 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70044.958587 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66114.279032 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67263.713741 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176 # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22469.301798 # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 20366.746845 # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22469.301798 # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20366.746845 # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959 # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10131.989012 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10134.836676 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10131.989012 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10134.836676 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10275.715047 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10220.729033 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10275.715047 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10220.729033 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69355.674069 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63675.021611 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69355.674069 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63675.021611 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68142.470667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65494.840344 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 969598 # Transaction distribution
sim_ticks 51728174627500 # Number of ticks simulated
final_tick 51728174627500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 184836 # Simulator instruction rate (inst/s)
-host_op_rate 217188 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10028441874 # Simulator tick rate (ticks/s)
-host_mem_usage 718288 # Number of bytes of host memory used
-host_seconds 5158.15 # Real time elapsed on the host
+host_inst_rate 121986 # Simulator instruction rate (inst/s)
+host_op_rate 143338 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6618487836 # Simulator tick rate (ticks/s)
+host_mem_usage 708088 # Number of bytes of host memory used
+host_seconds 7815.71 # Real time elapsed on the host
sim_insts 953410832 # Number of instructions simulated
sim_ops 1120287994 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker 394816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 334912 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 77628104 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 10241472 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 67386632 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 424256 # Number of bytes read from this memory
system.physmem.bytes_read::total 78782088 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 10241472 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 10241472 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 95103808 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.inst 20580 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 95124388 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 6169 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5233 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 1212952 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 160023 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1052929 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6629 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1230983 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1485997 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.inst 2573 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1488570 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 7633 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 6474 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 1500693 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 197986 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1302707 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8202 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1523002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 197986 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 197986 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1838530 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.inst 398 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1838928 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1838530 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 7633 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 6474 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1501091 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 197986 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1303104 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8202 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3361929 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1230983 # Number of read requests accepted
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 280461298998 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.bytes_read::cpu.inst 740 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 16 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.dcache.tags.sampled_refs 11209674 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 29.535631 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959689 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.999921 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.959689 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999921 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1391009936 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1391009936 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst 169770938 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 169770938 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 169770938 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst 152453541 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 152453541 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 152453541 # number of WriteReq hits
-system.cpu.dcache.WriteInvalidateReq_hits::cpu.inst 337498 # number of WriteInvalidateReq hits
+system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337498 # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total 337498 # number of WriteInvalidateReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst 4114364 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 4114364 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 4114364 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst 4358642 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 4358642 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 4358642 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst 322224479 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data 322224479 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 322224479 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst 322224479 # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data 322224479 # number of overall hits
system.cpu.dcache.overall_hits::total 322224479 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst 8085158 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data 8085158 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 8085158 # number of ReadReq misses
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 24725990 # number of replacements
system.cpu.l2cache.tags.occ_blocks::writebacks 36067.634498 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 340.939586 # Average occupied blocks per requestor
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21149756024 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28553765785 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.inst 12667521943 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 12667521943 # number of WriteInvalidateReq MSHR miss cycles
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 12667521943 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 390061961 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 390061961 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 390061961 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst 120500 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 44297743880 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44297743880 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44297743880 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 413632000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 355518000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72082359665 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6634859761 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65447499904 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 72851509665 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 413632000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 355518000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72082359665 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6634859761 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65447499904 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 72851509665 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 8006368251 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2718370250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5287998001 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8006368251 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 5177591000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5177591000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5177591000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 13183959251 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2718370250 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465589001 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13183959251 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.013704 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.044207 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013529 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.inst 0.434381 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.434381 # mshr miss rate for WriteInvalidateReq accesses
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.434381 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.782463 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782463 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782463 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.300989 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.300989 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.300989 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033495 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.105791 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.032638 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033495 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.105791 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.032638 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62767.963803 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61556.429568 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.920584 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62885.723377 # average ReadReq mshr miss latency
-system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.inst 23426.098011 # average WriteInvalidateReq mshr miss latency
+system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 23426.098011 # average WriteInvalidateReq mshr miss latency
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23426.098011 # average WriteInvalidateReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10009.545049 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.545049 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.545049 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 60250 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 61582.977042 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61582.977042 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61582.977042 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61556.429568 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62083.269607 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62034.399793 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61556.429568 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62083.269607 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 34111380 # Transaction distribution
---------- Begin Simulation Statistics ----------
-sim_seconds 5.125948 # Number of seconds simulated
-sim_ticks 5125948496500 # Number of ticks simulated
-final_tick 5125948496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.129943 # Number of seconds simulated
+sim_ticks 5129943020500 # Number of ticks simulated
+final_tick 5129943020500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 181287 # Simulator instruction rate (inst/s)
-host_op_rate 358347 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2277524092 # Simulator tick rate (ticks/s)
-host_mem_usage 808864 # Number of bytes of host memory used
-host_seconds 2250.67 # Real time elapsed on the host
-sim_insts 408017153 # Number of instructions simulated
-sim_ops 806519171 # Number of ops (including micro ops) simulated
+host_inst_rate 121408 # Simulator instruction rate (inst/s)
+host_op_rate 239988 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1526556123 # Simulator tick rate (ticks/s)
+host_mem_usage 798272 # Number of bytes of host memory used
+host_seconds 3360.47 # Real time elapsed on the host
+sim_insts 407987808 # Number of instructions simulated
+sim_ops 806471132 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1048640 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10814912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 4352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1049088 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10796544 # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11896448 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1048640 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1048640 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9598912 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9598912 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16385 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 168983 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 11878656 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1049088 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1049088 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9594624 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 68 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 16392 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 168696 # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 185882 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149983 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149983 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 812 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 204575 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2109836 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2320829 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 204575 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 204575 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1872612 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1872612 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1872612 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 204575 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2109836 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4193440 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 185882 # Number of read requests accepted
-system.physmem.writeReqs 196703 # Number of write requests accepted
-system.physmem.readBursts 185882 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 196703 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 11884864 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 11584 # Total number of bytes read from write queue
-system.physmem.bytesWritten 12459008 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11896448 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 12588992 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 181 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2006 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 1725 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11442 # Per bank write bursts
-system.physmem.perBankRdBursts::1 11010 # Per bank write bursts
-system.physmem.perBankRdBursts::2 11990 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11673 # Per bank write bursts
-system.physmem.perBankRdBursts::4 12100 # Per bank write bursts
-system.physmem.perBankRdBursts::5 11243 # Per bank write bursts
-system.physmem.perBankRdBursts::6 11527 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11544 # Per bank write bursts
-system.physmem.perBankRdBursts::8 11275 # Per bank write bursts
-system.physmem.perBankRdBursts::9 11901 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11758 # Per bank write bursts
-system.physmem.perBankRdBursts::11 11788 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11617 # Per bank write bursts
-system.physmem.perBankRdBursts::13 12244 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11799 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10790 # Per bank write bursts
-system.physmem.perBankWrBursts::0 14290 # Per bank write bursts
-system.physmem.perBankWrBursts::1 13466 # Per bank write bursts
-system.physmem.perBankWrBursts::2 12356 # Per bank write bursts
-system.physmem.perBankWrBursts::3 11306 # Per bank write bursts
-system.physmem.perBankWrBursts::4 11781 # Per bank write bursts
-system.physmem.perBankWrBursts::5 11472 # Per bank write bursts
-system.physmem.perBankWrBursts::6 11444 # Per bank write bursts
-system.physmem.perBankWrBursts::7 11849 # Per bank write bursts
-system.physmem.perBankWrBursts::8 11105 # Per bank write bursts
-system.physmem.perBankWrBursts::9 11337 # Per bank write bursts
-system.physmem.perBankWrBursts::10 12902 # Per bank write bursts
-system.physmem.perBankWrBursts::11 12297 # Per bank write bursts
-system.physmem.perBankWrBursts::12 12359 # Per bank write bursts
-system.physmem.perBankWrBursts::13 12104 # Per bank write bursts
-system.physmem.perBankWrBursts::14 12504 # Per bank write bursts
-system.physmem.perBankWrBursts::15 12100 # Per bank write bursts
+system.physmem.num_reads::total 185604 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 149916 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 848 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 204503 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2104613 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2315553 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 204503 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 204503 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1870318 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1870318 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1870318 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 848 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 204503 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2104613 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 5527 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4185871 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 185604 # Number of read requests accepted
+system.physmem.writeReqs 196636 # Number of write requests accepted
+system.physmem.readBursts 185604 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 196636 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 11865664 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 12992 # Total number of bytes read from write queue
+system.physmem.bytesWritten 12442240 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11878656 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 12584704 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 203 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 2199 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 1712 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 11483 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10958 # Per bank write bursts
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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-system.physmem.bytesPerActivate::640-767 2000 2.66% 82.59% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 10594 14.08% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 75254 # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 23.780866 # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::total 75289 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::116-119 3 0.04% 98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::120-123 10 0.13% 98.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.01% 98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 14 0.18% 98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 5 0.06% 98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.01% 98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 5 0.06% 98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 13 0.17% 99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 10 0.13% 99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 3 0.04% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 6 0.08% 99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 11 0.14% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167 3 0.04% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 2 0.03% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 1 0.01% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 7 0.09% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 2 0.03% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187 1 0.01% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 2 0.03% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 1 0.01% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203 2 0.03% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207 2 0.03% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219 2 0.03% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223 4 0.05% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227 2 0.03% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231 2 0.03% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-251 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 7808 # Writes before turning the bus around for reads
-system.physmem.totQLat 1993300749 # Total ticks spent queuing
-system.physmem.totMemAccLat 5475194499 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 928505000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10733.93 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::172-175 3 0.04% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 5 0.06% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::180-183 1 0.01% 99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::184-187 3 0.04% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::188-191 1 0.01% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::196-199 2 0.03% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::200-203 6 0.08% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207 3 0.04% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::216-219 1 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::220-223 1 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-227 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::228-231 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::244-247 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 7789 # Writes before turning the bus around for reads
+system.physmem.totQLat 1998636250 # Total ticks spent queuing
+system.physmem.totMemAccLat 5474905000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 927005000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10780.07 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29483.93 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29530.07 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.46 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.04 # Average write queue length when enqueuing
-system.physmem.readRowHits 152642 # Number of row buffer hits during reads
-system.physmem.writeRowHits 152476 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 78.31 # Row buffer hit rate for writes
-system.physmem.avgGap 13398195.03 # Average gap between requests
-system.physmem.pageHitRate 80.21 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 279704880 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 152616750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 721718400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 634806720 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 129444104115 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2962019880750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 3428054662095 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.765327 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 4927513863750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 171166580000 # Time in different power states
+system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.71 # Average write queue length when enqueuing
+system.physmem.readRowHits 152292 # Number of row buffer hits during reads
+system.physmem.writeRowHits 152229 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 78.29 # Row buffer hit rate for writes
+system.physmem.avgGap 13420738.20 # Average gap between requests
+system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 279697320 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 152612625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 719316000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 633329280 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 129572750835 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2964303640500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 3430724068320 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.764961 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 4931314948000 # Time in different power states
+system.physmem_0.memoryStateTime::REF 171299960000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 27267949750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 27328009000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 289215360 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 157806000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 726741600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 626667840 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 129734124390 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2961765477000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 3428101862670 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.774535 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 4927089550750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 171166580000 # Time in different power states
+system.physmem_1.actEnergy 289487520 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 157954500 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 726804000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 626447520 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 129789266760 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2964113714250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 3430766396310 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.773213 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 4930997374750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 171299960000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 27689450500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 27642592750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 86963954 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86963954 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 905408 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 80060833 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 78220075 # Number of BTB hits
+system.cpu.branchPred.lookups 86966196 # Number of BP lookups
+system.cpu.branchPred.condPredicted 86966196 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 908530 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 80060297 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 78222813 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.700801 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1554669 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 179026 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.704875 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1554803 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 179885 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 449722784 # number of cpu cycles simulated
+system.cpu.numCycles 449725865 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27725020 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 429300438 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86963954 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79774744 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 417978242 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1899598 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 143976 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 49214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 212054 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 124897 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 365 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9198894 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 449574 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 4910 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 447183567 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.894463 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.051838 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27729826 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 429316628 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86966196 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79777616 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 417943861 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1905694 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 153883 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 50061 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 216755 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 126625 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 694 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9209956 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 450181 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5437 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 447174552 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.894587 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.051890 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 281562684 62.96% 62.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2296710 0.51% 63.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 72185404 16.14% 79.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1608090 0.36% 79.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2152491 0.48% 80.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2328628 0.52% 80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1534045 0.34% 81.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1900420 0.42% 81.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 81615095 18.25% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 281545500 62.96% 62.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2299594 0.51% 63.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 72183543 16.14% 79.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1609599 0.36% 79.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2153830 0.48% 80.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2329535 0.52% 80.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1534724 0.34% 81.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1901427 0.43% 81.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 81616800 18.25% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 447183567 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.193372 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.954589 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 23075597 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 264910108 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 150816162 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 7431901 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 949799 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 838865197 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 949799 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 25926245 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 223342995 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 13219671 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 154710115 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 29034742 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 835373495 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 478818 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 12412845 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 182552 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 13765619 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 997850152 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1814454577 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1115386152 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 142 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964539686 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 33310464 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 468855 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 472576 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 39019315 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17353635 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10197147 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1310615 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1095058 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 829813890 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1210662 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 824509848 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 239912 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 23585262 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 36379120 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 154680 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 447183567 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.843784 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.418075 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 447174552 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.193376 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.954618 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 23090202 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 264882686 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 150813511 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 7435306 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 952847 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 838903899 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 952847 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 25942831 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 223326641 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 13232428 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 154708804 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 29011001 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 835406292 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 477425 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 12418228 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 176585 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 13740194 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 997876395 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1814508658 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1115444420 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 102 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964480017 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 33396376 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 469202 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 473127 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 39031385 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17359783 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10198929 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1317086 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1098616 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 829832373 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1210818 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 824505871 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 240863 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 23642425 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 36460999 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 154878 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 447174552 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.843812 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.418056 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 262867260 58.78% 58.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13875410 3.10% 61.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10102524 2.26% 64.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6917845 1.55% 65.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 74366987 16.63% 82.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4460507 1.00% 83.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72819289 16.28% 99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1200322 0.27% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 573423 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 262851560 58.78% 58.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13883927 3.10% 61.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10098896 2.26% 64.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6926055 1.55% 65.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 74362880 16.63% 82.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4459374 1.00% 83.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72818710 16.28% 99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1199863 0.27% 99.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 573287 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 447183567 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 447174552 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1986412 71.97% 71.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 252 0.01% 71.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 1233 0.04% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 612541 22.19% 94.22% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 159591 5.78% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1983031 71.93% 71.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 252 0.01% 71.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 1287 0.05% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 612199 22.21% 94.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 160068 5.81% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 292966 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 796097417 96.55% 96.59% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 150721 0.02% 96.61% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 125468 0.02% 96.62% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 294191 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 796088573 96.55% 96.59% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 150664 0.02% 96.61% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 125614 0.02% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 18437939 2.24% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9405337 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 18441786 2.24% 98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9405043 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 824509848 # Type of FU issued
-system.cpu.iq.rate 1.833374 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2760029 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.003347 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 2099202980 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 854622338 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 819935754 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 826976810 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1879265 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 824505871 # Type of FU issued
+system.cpu.iq.rate 1.833352 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2756837 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.003344 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 2099183812 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 854698119 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 819923286 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 181 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 182 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 826968435 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1878873 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3349902 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 15405 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14537 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1763571 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3357342 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 15595 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14483 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1769318 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2224753 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 72078 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2224742 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 72242 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 949799 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 205606066 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 9444034 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 831024552 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 186671 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17353635 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10197147 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 713788 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 414805 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 8129418 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14537 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 518368 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 539118 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1057486 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 822883825 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 18037381 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1492626 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 952847 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 205624678 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 9408932 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 831043191 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 186605 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17359783 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10198929 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 713805 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 415277 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 8093737 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14483 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 519848 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 541033 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1060881 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 822872781 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 18039155 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1498773 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 27216272 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83330623 # Number of branches executed
-system.cpu.iew.exec_stores 9178891 # Number of stores executed
-system.cpu.iew.exec_rate 1.829758 # Inst execution rate
-system.cpu.iew.wb_sent 822374066 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 819935816 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 641195588 # num instructions producing a value
-system.cpu.iew.wb_consumers 1050795800 # num instructions consuming a value
+system.cpu.iew.exec_refs 27216659 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83327917 # Number of branches executed
+system.cpu.iew.exec_stores 9177504 # Number of stores executed
+system.cpu.iew.exec_rate 1.829721 # Inst execution rate
+system.cpu.iew.wb_sent 822362005 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 819923336 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 641186937 # num instructions producing a value
+system.cpu.iew.wb_consumers 1050770759 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.823203 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.610200 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.823163 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.610206 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24410170 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1055982 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 917776 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 443513895 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.818476 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.675053 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 24478012 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1055940 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 920864 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 443494014 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.818449 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.675035 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 272662791 61.48% 61.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11205596 2.53% 64.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3584252 0.81% 64.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74566158 16.81% 81.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2433850 0.55% 82.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1609395 0.36% 82.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 952580 0.21% 82.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 71045442 16.02% 98.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5453831 1.23% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 272650089 61.48% 61.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11209358 2.53% 64.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3583153 0.81% 64.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74560256 16.81% 81.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2436163 0.55% 82.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1608243 0.36% 82.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 951229 0.21% 82.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 71042725 16.02% 98.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5452798 1.23% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 443513895 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 408017153 # Number of instructions committed
-system.cpu.commit.committedOps 806519171 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 443494014 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 407987808 # Number of instructions committed
+system.cpu.commit.committedOps 806471132 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22437308 # Number of memory references committed
-system.cpu.commit.loads 14003732 # Number of loads committed
-system.cpu.commit.membars 475345 # Number of memory barriers committed
-system.cpu.commit.branches 82208289 # Number of branches committed
+system.cpu.commit.refs 22432051 # Number of memory references committed
+system.cpu.commit.loads 14002440 # Number of loads committed
+system.cpu.commit.membars 475347 # Number of memory barriers committed
+system.cpu.commit.branches 82201961 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735327062 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1156001 # Number of function calls committed.
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system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction
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system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction
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system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.idleCycles 2539217 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9802174458 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 408017153 # Number of Instructions Simulated
-system.cpu.committedOps 806519171 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.102215 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.102215 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.907264 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.907264 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1092796597 # number of integer regfile reads
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-system.cpu.misc_regfile_writes 402877 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 1660514 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.996956 # Cycle average of tags in use
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-system.cpu.dcache.tags.sampled_refs 1661026 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11.529565 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 1268912158 # The number of ROB reads
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+system.cpu.idleCycles 2551313 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9810160420 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
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+system.cpu.cpi_total 1.102302 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 0.907192 # IPC: Total IPC of All Threads
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system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11605.245219 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11605.245219 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11605.245219 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11605.245219 # average overall miss latency
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+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11886.045299 # average overall miss latency
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system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
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-system.cpu.itb_walker_cache.writebacks::total 2894 # number of writebacks
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-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15060 # number of ReadReq MSHR misses
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-system.cpu.itb_walker_cache.overall_mshr_misses::total 15060 # number of overall MSHR misses
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-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 144633033 # number of demand (read+write) MSHR miss cycles
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-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 144633033 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 144633033 # number of overall MSHR miss cycles
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-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9603.787052 # average overall mshr miss latency
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-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9603.787052 # average overall mshr miss latency
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+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9884.988352 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.l2cache.tags.tagsinuse 64819.841328 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3843950 # Total number of references to valid blocks.
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-system.cpu.l2cache.tags.avg_refs 21.709014 # Average number of references to valid blocks.
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+system.cpu.l2cache.tags.avg_refs 21.680959 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50385.421591 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.865695 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.131540 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 3266.822655 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11149.599847 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000273 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50388.015751 # Average occupied blocks per requestor
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+system.cpu.l2cache.tags.occ_blocks::cpu.inst 3267.225445 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 567 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3385 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7409 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52637 # Occupied blocks per task id
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-system.cpu.l2cache.ReadReq_hits::total 2402250 # number of ReadReq hits
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-system.cpu.l2cache.Writeback_hits::total 1584244 # number of Writeback hits
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-system.cpu.l2cache.UpgradeReq_hits::total 297 # number of UpgradeReq hits
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-system.cpu.l2cache.overall_hits::total 2555667 # number of overall hits
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-system.cpu.l2cache.overall_miss_latency::cpu.inst 1248819000 # number of overall miss cycles
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-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12555 # number of ReadReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_accesses::cpu.data 1372965 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2454567 # number of ReadReq accesses(hits+misses)
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-system.cpu.l2cache.Writeback_accesses::total 1584244 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1759 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 1759 # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67868 # number of demand (read+write) accesses
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 3074514 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 111516357 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 225687 # Transaction distribution
-system.iobus.trans_dist::ReadResp 225687 # Transaction distribution
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system.iobus.trans_dist::WriteReq 57721 # Transaction distribution
system.iobus.trans_dist::WriteResp 11001 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
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system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes)
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-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 52371753 # Layer occupancy (ticks)
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system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47581 # number of replacements
-system.iocache.tags.tagsinuse 0.091546 # Cycle average of tags in use
+system.iocache.tags.replacements 47582 # number of replacements
+system.iocache.tags.tagsinuse 0.103930 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47597 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4992992715000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091546 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005722 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.005722 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 4992992710000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103930 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006496 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.006496 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428724 # Number of tag accesses
-system.iocache.tags.data_accesses 428724 # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide 916 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 916 # number of ReadReq misses
+system.iocache.tags.tag_accesses 428733 # Number of tag accesses
+system.iocache.tags.data_accesses 428733 # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide 917 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 917 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses
-system.iocache.demand_misses::total 916 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 916 # number of overall misses
-system.iocache.overall_misses::total 916 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149161446 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 149161446 # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12345702001 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 12345702001 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 149161446 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 149161446 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 149161446 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 149161446 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 917 # number of demand (read+write) misses
+system.iocache.demand_misses::total 917 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 917 # number of overall misses
+system.iocache.overall_misses::total 917 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152376946 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 152376946 # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12347668009 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 12347668009 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 152376946 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 152376946 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 152376946 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 152376946 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 917 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 917 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 916 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 917 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 917 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 917 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 917 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 162840.006550 # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264248.758583 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 264248.758583 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 162840.006550 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162840.006550 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 162840.006550 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 70237 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 166168.970556 # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264290.839234 # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 264290.839234 # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 166168.970556 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 166168.970556 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 70541 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 9120 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 9150 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 7.701425 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 7.709399 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 917 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 917 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 101504946 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9916256007 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9916256007 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 101504946 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101504946 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 101504946 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 917 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 917 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 917 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 917 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 104665946 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9918222015 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9918222015 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 104665946 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 104665946 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 110813.259825 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212248.630287 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212248.630287 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 110813.259825 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110813.259825 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 110813.259825 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 114139.526718 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212290.710938 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212290.710938 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 662646 # Transaction distribution
-system.membus.trans_dist::ReadResp 662640 # Transaction distribution
-system.membus.trans_dist::WriteReq 13889 # Transaction distribution
-system.membus.trans_dist::WriteResp 13889 # Transaction distribution
-system.membus.trans_dist::Writeback 149983 # Transaction distribution
+system.membus.trans_dist::ReadReq 662691 # Transaction distribution
+system.membus.trans_dist::ReadResp 662685 # Transaction distribution
+system.membus.trans_dist::WriteReq 13891 # Transaction distribution
+system.membus.trans_dist::WriteResp 13891 # Transaction distribution
+system.membus.trans_dist::Writeback 149916 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2187 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1743 # Transaction distribution
-system.membus.trans_dist::ReadExReq 133791 # Transaction distribution
-system.membus.trans_dist::ReadExResp 133789 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2202 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1731 # Transaction distribution
+system.membus.trans_dist::ReadExReq 133471 # Transaction distribution
+system.membus.trans_dist::ReadExResp 133469 # Transaction distribution
system.membus.trans_dist::MessageReq 1644 # Transaction distribution
system.membus.trans_dist::MessageResp 1644 # Transaction distribution
system.membus.trans_dist::BadAddressError 6 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478766 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478147 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1725388 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141466 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 141466 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1870142 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724773 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1869528 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18480320 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20272507 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18458240 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20250435 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 26284203 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 1595 # Total snoops (count)
-system.membus.snoop_fanout::samples 385911 # Request fanout histogram
+system.membus.pkt_size::total 26262131 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 1626 # Total snoops (count)
+system.membus.snoop_fanout::samples 385584 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 385911 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 385584 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 385911 # Request fanout histogram
-system.membus.reqLayer0.occupancy 251714500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 385584 # Request fanout histogram
+system.membus.reqLayer0.occupancy 251730500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 583067000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 583066500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1996777999 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1995956000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 7500 # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy 7000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 3163999272 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 3161502789 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer4.occupancy 54979247 # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy 54989497 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
use_default_range=false
width=8
default=system.pc.pciconfig.pio
-master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave
+master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.ruby.l1_cntrl0.sequencer.pio_slave_port system.ruby.l1_cntrl1.sequencer.pio_slave_port system.ruby.io_controller.dma_sequencer.slave
slave=system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port system.ruby.l1_cntrl1.sequencer.pio_master_port system.ruby.l1_cntrl1.sequencer.mem_master_port
[system.mem_ctrls]
[system.pc]
type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge
+children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge
eventq_index=0
intrctrl=system.intrctrl
system=system
system=system
update_data=false
warn_access=
-pio=system.iobus.master[11]
+pio=system.iobus.master[12]
[system.pc.com_1]
type=Uart8250
platform=system.pc
system=system
terminal=system.pc.com_1.terminal
-pio=system.iobus.master[12]
+pio=system.iobus.master[13]
[system.pc.com_1.terminal]
type=Terminal
system=system
update_data=false
warn_access=
-pio=system.iobus.master[13]
+pio=system.iobus.master[14]
[system.pc.fake_com_3]
type=IsaFake
system=system
update_data=false
warn_access=
-pio=system.iobus.master[14]
+pio=system.iobus.master[15]
[system.pc.fake_com_4]
type=IsaFake
system=system
update_data=false
warn_access=
-pio=system.iobus.master[15]
+pio=system.iobus.master[16]
[system.pc.fake_floppy]
type=IsaFake
system=system
update_data=false
warn_access=
-pio=system.iobus.master[16]
+pio=system.iobus.master[17]
-[system.pc.i_dont_exist]
+[system.pc.i_dont_exist1]
type=IsaFake
clk_domain=system.clk_domain
eventq_index=0
warn_access=
pio=system.iobus.master[10]
+[system.pc.i_dont_exist2]
+type=IsaFake
+clk_domain=system.clk_domain
+eventq_index=0
+fake_mem=false
+pio_addr=9223372036854776045
+pio_latency=100000
+pio_size=1
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.iobus.master[11]
+
[system.pc.pciconfig]
type=PciConfigAll
bus=0
system=system
using_ruby_tester=false
version=1
-slave=system.iobus.master[19]
+slave=system.iobus.master[20]
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
prefetcher=system.ruby.l1_cntrl0.prefetcher
recycle_latency=10
ruby_system=system.ruby
-send_evictions=false
+send_evictions=true
sequencer=system.ruby.l1_cntrl0.sequencer
system=system
to_l2_latency=1
master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
mem_master_port=system.iobus.slave[2]
pio_master_port=system.iobus.slave[1]
-pio_slave_port=system.iobus.master[17]
+pio_slave_port=system.iobus.master[18]
slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master
[system.ruby.l1_cntrl1]
prefetcher=system.ruby.l1_cntrl1.prefetcher
recycle_latency=10
ruby_system=system.ruby
-send_evictions=false
+send_evictions=true
sequencer=system.ruby.l1_cntrl1.sequencer
system=system
to_l2_latency=1
master=system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave
mem_master_port=system.iobus.slave[4]
pio_master_port=system.iobus.slave[3]
-pio_slave_port=system.iobus.master[18]
+pio_slave_port=system.iobus.master[19]
slave=system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.interrupts.int_master
[system.ruby.l2_cntrl0]
---------- Begin Simulation Statistics ----------
-sim_seconds 2.221319 # Number of seconds simulated
-sim_ticks 4442638390 # Number of ticks simulated
-final_tick 4442638390 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.233778 # Number of seconds simulated
+sim_ticks 4467555024 # Number of ticks simulated
+final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 2000000000 # Frequency of simulated ticks
-host_inst_rate 1901707 # Simulator instruction rate (inst/s)
-host_op_rate 1902455 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3812734 # Simulator tick rate (ticks/s)
-host_mem_usage 568684 # Number of bytes of host memory used
-host_seconds 1165.21 # Real time elapsed on the host
-sim_insts 2215889371 # Number of instructions simulated
-sim_ops 2216760815 # Number of ops (including micro ops) simulated
+host_inst_rate 1794168 # Simulator instruction rate (inst/s)
+host_op_rate 1794873 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3597181 # Simulator tick rate (ticks/s)
+host_mem_usage 569892 # Number of bytes of host memory used
+host_seconds 1241.96 # Real time elapsed on the host
+sim_insts 2228284650 # Number of instructions simulated
+sim_ops 2229160714 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 2 # Clock period in ticks
system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
-system.hypervisor_desc.bw_read::cpu.data 7559 # Total read bandwidth from this memory (bytes/s)
-system.hypervisor_desc.bw_read::total 7559 # Total read bandwidth from this memory (bytes/s)
-system.hypervisor_desc.bw_total::cpu.data 7559 # Total bandwidth to/from this memory (bytes/s)
-system.hypervisor_desc.bw_total::total 7559 # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
-system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
-system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
-system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
-system.partition_desc.bw_read::cpu.data 2182 # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_read::total 2182 # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_total::cpu.data 2182 # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bw_total::total 2182 # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.bytes_read::cpu.inst 8278734588 # Number of bytes read from this memory
-system.physmem1.bytes_read::cpu.data 1487826857 # Number of bytes read from this memory
-system.physmem1.bytes_read::total 9766561445 # Number of bytes read from this memory
-system.physmem1.bytes_inst_read::cpu.inst 8278734588 # Number of instructions bytes read from this memory
-system.physmem1.bytes_inst_read::total 8278734588 # Number of instructions bytes read from this memory
-system.physmem1.bytes_written::cpu.data 890413424 # Number of bytes written to this memory
-system.physmem1.bytes_written::total 890413424 # Number of bytes written to this memory
-system.physmem1.num_reads::cpu.inst 2069683647 # Number of read requests responded to by this memory
-system.physmem1.num_reads::cpu.data 322864285 # Number of read requests responded to by this memory
-system.physmem1.num_reads::total 2392547932 # Number of read requests responded to by this memory
-system.physmem1.num_writes::cpu.data 186352766 # Number of write requests responded to by this memory
-system.physmem1.num_writes::total 186352766 # Number of write requests responded to by this memory
-system.physmem1.num_other::cpu.data 5352814 # Number of other requests responded to by this memory
-system.physmem1.num_other::total 5352814 # Number of other requests responded to by this memory
-system.physmem1.bw_read::cpu.inst 3726945054 # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_read::cpu.data 669794265 # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_read::total 4396739319 # Total read bandwidth from this memory (bytes/s)
-system.physmem1.bw_inst_read::cpu.inst 3726945054 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem1.bw_inst_read::total 3726945054 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem1.bw_write::cpu.data 400848931 # Write bandwidth from this memory (bytes/s)
-system.physmem1.bw_write::total 400848931 # Write bandwidth from this memory (bytes/s)
-system.physmem1.bw_total::cpu.inst 3726945054 # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.bw_total::cpu.data 1070643195 # Total bandwidth to/from this memory (bytes/s)
-system.physmem1.bw_total::total 4797588250 # Total bandwidth to/from this memory (bytes/s)
-system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
-system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
-system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
-system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
-system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
-system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
-system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
-system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
-system.rom.bw_read::cpu.inst 194612 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::cpu.data 313504 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::total 508116 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::cpu.inst 194612 # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::total 194612 # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_total::cpu.inst 194612 # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::cpu.data 313504 # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::total 508116 # Total bandwidth to/from this memory (bytes/s)
+system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s)
+system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s)
+system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s)
+system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s)
system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
system.nvram.bytes_read::total 284 # Number of bytes read from this memory
system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
-system.nvram.bw_read::cpu.data 128 # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_read::total 128 # Total read bandwidth from this memory (bytes/s)
+system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s)
+system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s)
system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_total::cpu.data 169 # Total bandwidth to/from this memory (bytes/s)
-system.nvram.bw_total::total 169 # Total bandwidth to/from this memory (bytes/s)
-system.physmem0.bytes_read::cpu.inst 601850192 # Number of bytes read from this memory
-system.physmem0.bytes_read::cpu.data 95637362 # Number of bytes read from this memory
-system.physmem0.bytes_read::total 697487554 # Number of bytes read from this memory
-system.physmem0.bytes_inst_read::cpu.inst 601850192 # Number of instructions bytes read from this memory
-system.physmem0.bytes_inst_read::total 601850192 # Number of instructions bytes read from this memory
-system.physmem0.bytes_written::cpu.data 15105383 # Number of bytes written to this memory
-system.physmem0.bytes_written::total 15105383 # Number of bytes written to this memory
-system.physmem0.num_reads::cpu.inst 150462548 # Number of read requests responded to by this memory
-system.physmem0.num_reads::cpu.data 11907116 # Number of read requests responded to by this memory
-system.physmem0.num_reads::total 162369664 # Number of read requests responded to by this memory
-system.physmem0.num_writes::cpu.data 1890212 # Number of write requests responded to by this memory
-system.physmem0.num_writes::total 1890212 # Number of write requests responded to by this memory
+system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
+system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
+system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
+system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
+system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
+system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
+system.physmem0.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
+system.physmem0.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
+system.physmem0.bytes_read::total 709825348 # Number of bytes read from this memory
+system.physmem0.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
+system.physmem0.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
+system.physmem0.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
+system.physmem0.bytes_written::total 15400223 # Number of bytes written to this memory
+system.physmem0.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
+system.physmem0.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
+system.physmem0.num_reads::total 165224885 # Number of read requests responded to by this memory
+system.physmem0.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
+system.physmem0.num_writes::total 1927067 # Number of write requests responded to by this memory
system.physmem0.num_other::cpu.data 14 # Number of other requests responded to by this memory
system.physmem0.num_other::total 14 # Number of other requests responded to by this memory
-system.physmem0.bw_read::cpu.inst 270942687 # Total read bandwidth from this memory (bytes/s)
-system.physmem0.bw_read::cpu.data 43054309 # Total read bandwidth from this memory (bytes/s)
-system.physmem0.bw_read::total 313996996 # Total read bandwidth from this memory (bytes/s)
-system.physmem0.bw_inst_read::cpu.inst 270942687 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem0.bw_inst_read::total 270942687 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem0.bw_write::cpu.data 6800186 # Write bandwidth from this memory (bytes/s)
-system.physmem0.bw_write::total 6800186 # Write bandwidth from this memory (bytes/s)
-system.physmem0.bw_total::cpu.inst 270942687 # Total bandwidth to/from this memory (bytes/s)
-system.physmem0.bw_total::cpu.data 49854494 # Total bandwidth to/from this memory (bytes/s)
-system.physmem0.bw_total::total 320797182 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 2559471185 # Transaction distribution
-system.membus.trans_dist::ReadResp 2559471185 # Transaction distribution
-system.membus.trans_dist::WriteReq 188250351 # Transaction distribution
-system.membus.trans_dist::WriteResp 188250351 # Transaction distribution
-system.membus.trans_dist::SwapReq 5352828 # Transaction distribution
-system.membus.trans_dist::SwapResp 5352828 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.rom.port 216148 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::system.physmem0.port 300925096 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::system.physmem1.port 4139367294 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 4440508538 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.t1000.iob.pio 64 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.t1000.htod.pio 32 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.bridge.slave 8711566 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.rom.port 174098 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.nvram.port 752 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.hypervisor_desc.port 18048 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.partition_desc.port 1216 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem0.port 27594684 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem1.port 1029139730 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 1065640190 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5506148728 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.rom.port 432296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem0.port 601850192 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem1.port 8278734588 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 8881017076 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.t1000.iob.pio 256 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.t1000.htod.pio 128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.bridge.slave 34744011 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.rom.port 696392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.nvram.port 376 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.hypervisor_desc.port 16792 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.partition_desc.port 4846 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem0.port 110742969 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem1.port 2439206055 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 2585411825 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 11466428901 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 2753074364 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.806464 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.395070 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 532820095 19.35% 19.35% # Request fanout histogram
-system.membus.snoop_fanout::1 2220254269 80.65% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2753074364 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 4348534 # Transaction distribution
-system.iobus.trans_dist::ReadResp 4348534 # Transaction distribution
-system.iobus.trans_dist::WriteReq 7249 # Transaction distribution
-system.iobus.trans_dist::WriteResp 7249 # Transaction distribution
+system.physmem0.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s)
+system.physmem0.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s)
+system.physmem0.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s)
+system.physmem0.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem0.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem0.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s)
+system.physmem0.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s)
+system.physmem0.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s)
+system.physmem0.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s)
+system.physmem0.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s)
+system.physmem1.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
+system.physmem1.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
+system.physmem1.bytes_read::total 9813991967 # Number of bytes read from this memory
+system.physmem1.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
+system.physmem1.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
+system.physmem1.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
+system.physmem1.bytes_written::total 897268422 # Number of bytes written to this memory
+system.physmem1.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
+system.physmem1.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
+system.physmem1.num_reads::total 2403489130 # Number of read requests responded to by this memory
+system.physmem1.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
+system.physmem1.num_writes::total 187387796 # Number of write requests responded to by this memory
+system.physmem1.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
+system.physmem1.num_other::total 5403067 # Number of other requests responded to by this memory
+system.physmem1.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
+system.physmem1.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
+system.physmem1.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
+system.physmem1.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem1.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem1.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
+system.physmem1.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
+system.physmem1.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
+system.physmem1.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
+system.physmem1.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
+system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
+system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
+system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
+system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
+system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
+system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
+system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
+system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
+system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s)
+system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s)
+system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s)
+system.cpu_clk_domain.clock 2 # Clock period in ticks
+system.cpu.numCycles 2233777513 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 2228284650 # Number of instructions committed
+system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
+system.cpu.num_func_calls 44037246 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1839325658 # number of integer instructions
+system.cpu.num_fp_insts 14608322 # number of float instructions
+system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read
+system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written
+system.cpu.num_mem_refs 547951940 # number of memory refs
+system.cpu.num_load_insts 349807670 # Number of load instructions
+system.cpu.num_store_insts 198144270 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 2233777513 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.Branches 441057355 # Number of branches fetched
+system.cpu.op_class::No_OpClass 49673656 2.22% 2.22% # Class of executed instruction
+system.cpu.op_class::IntAlu 1619015933 72.49% 74.71% # Class of executed instruction
+system.cpu.op_class::IntMult 0 0.00% 74.71% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 74.71% # Class of executed instruction
+system.cpu.op_class::FloatAdd 8419779 0.38% 75.09% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.09% # Class of executed instruction
+system.cpu.op_class::MemRead 356274529 15.95% 91.04% # Class of executed instruction
+system.cpu.op_class::MemWrite 200199782 8.96% 100.00% # Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
+system.cpu.op_class::total 2233583679 # Class of executed instruction
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.iobus.trans_dist::ReadReq 4348554 # Transaction distribution
+system.iobus.trans_dist::ReadResp 4348554 # Transaction distribution
+system.iobus.trans_dist::WriteReq 7569 # Transaction distribution
+system.iobus.trans_dist::WriteResp 7569 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_membnks.pio 40 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_3.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_l2esr_4.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.t1000.fake_jbi.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.t1000.puart0.pio 29178 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.t1000.puart0.pio 29218 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.t1000.hvuart.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.disk0.pio 8682242 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 8711566 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.disk0.pio 8682882 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 8712246 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_membnks.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_1.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2_2.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_3.pio 16 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_l2esr_4.pio 16 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.t1000.fake_jbi.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.t1000.puart0.pio 14589 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.t1000.puart0.pio 14609 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.t1000.hvuart.pio 18 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.disk0.pio 34728964 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 34744011 # Cumulative packet size per connected master and slave (bytes)
-system.cpu_clk_domain.clock 2 # Clock period in ticks
-system.cpu.numCycles 2221319196 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 2215889371 # Number of instructions committed
-system.cpu.committedOps 2216760815 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1828751674 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 14599184 # Number of float alu accesses
-system.cpu.num_func_calls 43845838 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 314910579 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1828751674 # number of integer instructions
-system.cpu.num_fp_insts 14599184 # number of float instructions
-system.cpu.num_int_register_reads 4280788221 # number of times the integer registers were read
-system.cpu.num_int_register_writes 2088786554 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 35382311 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 22904834 # number of times the floating registers were written
-system.cpu.num_mem_refs 545231836 # number of memory refs
-system.cpu.num_load_insts 348274583 # Number of load instructions
-system.cpu.num_store_insts 196957253 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 2221319196 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 439059324 # Number of branches fetched
-system.cpu.op_class::No_OpClass 49315635 2.22% 2.22% # Class of executed instruction
-system.cpu.op_class::IntAlu 1609688995 72.47% 74.69% # Class of executed instruction
-system.cpu.op_class::IntMult 0 0.00% 74.69% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 74.69% # Class of executed instruction
-system.cpu.op_class::FloatAdd 8416009 0.38% 75.07% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.07% # Class of executed instruction
-system.cpu.op_class::MemRead 354694578 15.97% 91.04% # Class of executed instruction
-system.cpu.op_class::MemWrite 199010496 8.96% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 2221125713 # Class of executed instruction
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.iobus.pkt_size_system.bridge.master::system.disk0.pio 34731524 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 34746591 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 2573267624 # Transaction distribution
+system.membus.trans_dist::ReadResp 2573267624 # Transaction distribution
+system.membus.trans_dist::WriteReq 189322556 # Transaction distribution
+system.membus.trans_dist::WriteResp 189322556 # Transaction distribution
+system.membus.trans_dist::SwapReq 5403081 # Transaction distribution
+system.membus.trans_dist::SwapResp 5403081 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.rom.port 216148 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.physmem0.port 306145662 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.physmem1.port 4159053420 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 4465415230 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.t1000.iob.pio 64 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.t1000.htod.pio 32 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.bridge.slave 8712246 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.rom.port 174098 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.nvram.port 752 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.hypervisor_desc.port 18048 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.partition_desc.port 1216 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem0.port 28158270 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem1.port 1033506566 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 1070571292 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5535986522 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.rom.port 432296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem0.port 612291324 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem1.port 8318106840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 8930830460 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.t1000.iob.pio 256 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.t1000.htod.pio 128 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.bridge.slave 34746591 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.rom.port 696392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.nvram.port 376 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.hypervisor_desc.port 16792 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.partition_desc.port 4846 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem0.port 112934471 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem1.port 2454584131 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 2602983983 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 11533814443 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 2767993261 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.806616 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.394951 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 535285646 19.34% 19.34% # Request fanout histogram
+system.membus.snoop_fanout::1 2232707615 80.66% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 2767993261 # Request fanout histogram
---------- End Simulation Statistics ----------
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=mcf mcf.in
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 61493732000 # Number of ticks simulated
final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 271090 # Simulator instruction rate (inst/s)
-host_op_rate 272440 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 183993432 # Simulator tick rate (ticks/s)
-host_mem_usage 445016 # Number of bytes of host memory used
-host_seconds 334.22 # Real time elapsed on the host
+host_inst_rate 144123 # Simulator instruction rate (inst/s)
+host_op_rate 144840 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 97818525 # Simulator tick rate (ticks/s)
+host_mem_usage 433504 # Number of bytes of host memory used
+host_seconds 628.65 # Real time elapsed on the host
sim_insts 90602849 # Number of instructions simulated
sim_ops 91054080 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 996800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 49600 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 947200 # Number of bytes read from this memory
system.physmem.bytes_read::total 996800 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 49600 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 49600 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 15575 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory
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system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu.l2cache.tags]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 410940483000 # Number of ticks simulated
final_tick 410940483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 339016 # Simulator instruction rate (inst/s)
-host_op_rate 339016 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 227676015 # Simulator tick rate (ticks/s)
-host_mem_usage 297088 # Number of bytes of host memory used
-host_seconds 1804.94 # Real time elapsed on the host
+host_inst_rate 207244 # Simulator instruction rate (inst/s)
+host_op_rate 207244 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 139181064 # Simulator tick rate (ticks/s)
+host_mem_usage 283892 # Number of bytes of host memory used
+host_seconds 2952.56 # Real time elapsed on the host
sim_insts 611901617 # Number of instructions simulated
sim_ops 611901617 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 24320576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 171008 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24149568 # Number of bytes read from this memory
system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18724416 # Number of bytes written to this memory
system.physmem.bytes_written::total 18724416 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 380009 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2672 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 292569 # Number of write requests responded to by this memory
system.physmem.num_writes::total 292569 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 59182721 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 59182721 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 416138 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 416138 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 45564788 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 45564788 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 45564788 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 59182721 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 104747509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 380009 # Number of read requests accepted
system.physmem.writeReqs 292569 # Number of write requests accepted
system.cpu.dcache.tags.sampled_refs 2539546 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 79.790324 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.778260 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.997993 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 414706244 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 414706244 # Number of data accesses
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system.cpu.dcache.overall_hits::total 202631199 # number of overall hits
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system.cpu.dcache.ReadReq_misses::total 1908330 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::total 1543820 # number of WriteReq misses
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system.cpu.dcache.overall_misses::total 3452150 # number of overall misses
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system.cpu.dcache.demand_miss_latency::total 81320730750 # number of demand (read+write) miss cycles
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system.cpu.dcache.ReadReq_accesses::total 148873315 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.overall_accesses::total 206083349 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19082.041759 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total 19082.041759 # average ReadReq miss latency
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+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29087.521861 # average WriteReq miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.298304 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 1766435 # Transaction distribution
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 365317233000 # Number of ticks simulated
final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 241300 # Simulator instruction rate (inst/s)
-host_op_rate 261360 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 174011250 # Simulator tick rate (ticks/s)
-host_mem_usage 315696 # Number of bytes of host memory used
-host_seconds 2099.39 # Real time elapsed on the host
+host_inst_rate 157262 # Simulator instruction rate (inst/s)
+host_op_rate 170335 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 113407877 # Simulator tick rate (ticks/s)
+host_mem_usage 304680 # Number of bytes of host memory used
+host_seconds 3221.27 # Real time elapsed on the host
sim_insts 506582155 # Number of instructions simulated
sim_ops 548695378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory
system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory
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system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory
system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 25254894 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 144157 # Number of read requests accepted
system.physmem.writeReqs 96561 # Number of write requests accepted
system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 346818362 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses
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system.cpu.dcache.overall_avg_miss_latency::total 22007.254782 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1068525 # number of writebacks
system.cpu.dcache.writebacks::total 1068525 # number of writebacks
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294 # average ReadExReq mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu.l2cache.tags]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 226818771000 # Number of ticks simulated
final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 333141 # Simulator instruction rate (inst/s)
-host_op_rate 333141 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 189539219 # Simulator tick rate (ticks/s)
-host_mem_usage 300760 # Number of bytes of host memory used
-host_seconds 1196.69 # Real time elapsed on the host
+host_inst_rate 207340 # Simulator instruction rate (inst/s)
+host_op_rate 207340 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 117965343 # Simulator tick rate (ticks/s)
+host_mem_usage 287544 # Number of bytes of host memory used
+host_seconds 1922.76 # Real time elapsed on the host
sim_insts 398664665 # Number of instructions simulated
sim_ops 398664665 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 503872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory
system.physmem.bytes_read::total 503872 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 7873 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2221474 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1099027 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2221474 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1099027 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1099027 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2221474 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1099027 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1122447 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2221474 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7873 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.955330 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.803700 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 3291.955330 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst 94513823 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 94513823 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::total 73514792 # number of WriteReq hits
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system.cpu.dcache.overall_hits::total 168028615 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst 1181 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 1181 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst 5938 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 5938 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst 7119 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 216828260500 # Number of ticks simulated
final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_seconds 1558.09 # Real time elapsed on the host
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sim_insts 273037856 # Number of instructions simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7585 # Number of read requests accepted
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system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks
system.cpu.dcache.writebacks::total 1010 # number of writebacks
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=1
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
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+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu.l2cache.tags]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 559961514500 # Number of ticks simulated
final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 343254 # Simulator instruction rate (inst/s)
-host_op_rate 343254 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 206945650 # Simulator tick rate (ticks/s)
-host_mem_usage 305268 # Number of bytes of host memory used
-host_seconds 2705.84 # Real time elapsed on the host
+host_inst_rate 216839 # Simulator instruction rate (inst/s)
+host_op_rate 216839 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 130731039 # Simulator tick rate (ticks/s)
+host_mem_usage 291560 # Number of bytes of host memory used
+host_seconds 4283.31 # Real time elapsed on the host
sim_insts 928789150 # Number of instructions simulated
sim_ops 928789150 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 18657216 # Number of bytes read from this memory
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system.physmem.bytes_read::total 18657216 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 291519 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 33318747 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 333623 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 32985124 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s)
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system.cpu.l2cache.ReadReq_avg_miss_latency::total 72831.601399 # average ReadReq miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 73601.776670 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 114048 # number of writebacks
system.cpu.l2cache.writebacks::total 114048 # number of writebacks
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system.cpu.l2cache.overall_mshr_miss_latency::total 10124642750 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 217149 # Transaction distribution
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 57815555000 # Number of ticks simulated
final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 199176 # Simulator instruction rate (inst/s)
-host_op_rate 254717 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 162383906 # Simulator tick rate (ticks/s)
-host_mem_usage 320240 # Number of bytes of host memory used
-host_seconds 356.04 # Real time elapsed on the host
+host_inst_rate 131971 # Simulator instruction rate (inst/s)
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+host_mem_usage 309228 # Number of bytes of host memory used
+host_seconds 537.35 # Real time elapsed on the host
sim_insts 70915127 # Number of instructions simulated
sim_ops 90690083 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory
system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory
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system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory
system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory
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system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 128872 # Number of read requests accepted
system.physmem.writeReqs 83951 # Number of write requests accepted
system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.tags.occ_percent::cpu.inst 0.993306 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks
system.cpu.dcache.writebacks::total 128441 # number of writebacks
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system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits
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addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu.l2cache.tags]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 1199774280000 # Number of ticks simulated
final_tick 1199774280000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 344306 # Simulator instruction rate (inst/s)
-host_op_rate 344306 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 226179780 # Simulator tick rate (ticks/s)
-host_mem_usage 294788 # Number of bytes of host memory used
-host_seconds 5304.52 # Real time elapsed on the host
+host_inst_rate 216625 # Simulator instruction rate (inst/s)
+host_op_rate 216625 # Simulator op (including micro ops) rate (op/s)
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+host_mem_usage 282608 # Number of bytes of host memory used
+host_seconds 8431.08 # Real time elapsed on the host
sim_insts 1826378509 # Number of instructions simulated
sim_ops 1826378509 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 125505984 # Number of bytes read from this memory
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system.physmem.bytes_read::total 125505984 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory
system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory
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system.physmem.num_reads::total 1961031 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 104607997 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 104607997 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 51156 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 51156 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 54316457 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 54316457 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 54316457 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 158924454 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1961031 # Number of read requests accepted
system.physmem.writeReqs 1018242 # Number of write requests accepted
system.cpu.dcache.tags.sampled_refs 9126093 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.945917 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 16789907000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_percent::total 0.996259 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1231839903 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1231839903 # Number of data accesses
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system.cpu.dcache.overall_avg_miss_latency::total 29280.887712 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3700624 # number of writebacks
system.cpu.dcache.writebacks::total 3700624 # number of writebacks
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
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max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
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devices_per_rank=8
dll=true
eventq_index=0
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final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138724544500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45360250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138679184250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171103 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171014 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171103 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423125 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423125 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423125 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.222741 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.222741 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67170.422532 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57636.912325 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67176.402270 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67981.689072 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67981.689072 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu.l2cache.tags]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 52167245000 # Number of ticks simulated
final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 368966 # Simulator instruction rate (inst/s)
-host_op_rate 368966 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 209437459 # Simulator tick rate (ticks/s)
-host_mem_usage 299464 # Number of bytes of host memory used
-host_seconds 249.08 # Real time elapsed on the host
+host_inst_rate 211928 # Simulator instruction rate (inst/s)
+host_op_rate 211928 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 120297341 # Simulator tick rate (ticks/s)
+host_mem_usage 286252 # Number of bytes of host memory used
+host_seconds 433.65 # Real time elapsed on the host
sim_insts 91903089 # Number of instructions simulated
sim_ops 91903089 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 340352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory
system.physmem.bytes_read::total 340352 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 5318 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory
system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 6524247 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 3885350 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2638897 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 6524247 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 3885350 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 3885350 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 6524247 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 3885350 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2638897 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6524247 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 5318 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.700214 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.353687 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 53145366 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 53145366 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst 20069946 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 20069946 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20069946 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits
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system.cpu.dcache.demand_hits::total 26568138 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::total 26568138 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst 2911 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 2911 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst 3430 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::total 3430 # number of overall misses
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system.cpu.dcache.overall_miss_latency::total 232730000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst 20070465 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.overall_accesses::total 26571568 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses
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-system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 72609.826590 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72609.826590 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency
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-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67851.311953 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67851.311953 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 34 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 34 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 34 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1166 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1166 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1166 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst 1200 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits
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system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 34103500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 117640500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 151744000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151744000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 151744000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 70316.494845 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70316.494845 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70316.494845 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67415.759312 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68046.636771 # average overall mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68046.636771 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 13871 # number of replacements
system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.053168 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.017125 # Average occupied blocks per requestor
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system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831 # average ReadExReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
sim_ticks 131745950000 # Number of ticks simulated
final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 246838 # Simulator instruction rate (inst/s)
-host_op_rate 260207 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 188720644 # Simulator tick rate (ticks/s)
-host_mem_usage 315756 # Number of bytes of host memory used
-host_seconds 698.10 # Real time elapsed on the host
+host_inst_rate 165378 # Simulator instruction rate (inst/s)
+host_op_rate 174335 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 126440065 # Simulator tick rate (ticks/s)
+host_mem_usage 304748 # Number of bytes of host memory used
+host_seconds 1041.96 # Real time elapsed on the host
sim_insts 172317809 # Number of instructions simulated
sim_ops 181650742 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 247488 # Number of bytes read from this memory
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system.physmem.bytes_read::total 247488 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory
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system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory
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system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1878525 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 3867 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 1377.772724 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.336370 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst 28355530 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst 22407 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst 22407 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
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system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2778 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2160 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1090 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3868 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2160 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3868 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2160 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155790000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118562000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 37228000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 61501500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61501500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 217291500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118562000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 98729500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 217291500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118562000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 98729500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512735 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.992714 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.593616 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56079.913607 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56423.394495 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56176.706308 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
eventq_index=0
init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=/work/gem5.latest/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
eventq_index=0
init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=/work/gem5.latest/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=atomic
mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu0.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu0.l2cache.tags]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu1.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu1.l2cache.tags]
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=atomic
mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu0.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu0.l2cache.tags]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu1.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu1.l2cache.tags]
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=atomic
mem_ranges=2147483648:2415919103
-memories=system.realview.nvmem system.physmem system.realview.vram
+memories=system.physmem system.realview.nvmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu0.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu0.l2cache.tags]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu1.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu1.l2cache.tags]
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=atomic
mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu0.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu0.l2cache.tags]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu1.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu1.l2cache.tags]
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=timing
mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 34993500 # Number of ticks simulated
final_tick 34993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 162128 # Simulator instruction rate (inst/s)
-host_op_rate 162075 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 885888965 # Simulator tick rate (ticks/s)
-host_mem_usage 292456 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 25302 # Simulator instruction rate (inst/s)
+host_op_rate 25300 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 138325772 # Simulator tick rate (ticks/s)
+host_mem_usage 279800 # Number of bytes of host memory used
+host_seconds 0.25 # Real time elapsed on the host
sim_insts 6400 # Number of instructions simulated
sim_ops 6400 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 34112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 23296 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory
system.physmem.bytes_read::total 34112 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 974809607 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 665723634 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 309085973 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 974809607 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 665723634 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 665723634 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 974809607 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 665723634 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 309085973 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 974809607 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 533 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 104.036694 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.025400 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 104.036694 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.025400 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025400 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst 1233 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 1233 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst 1973 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data 1973 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst 1973 # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data 1973 # number of overall hits
system.cpu.dcache.overall_hits::total 1973 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses
system.cpu.dcache.overall_misses::total 227 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 7703250 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8670250 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 8670250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8670250 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst 16373500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 16373500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 16373500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst 16373500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 16373500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 1335 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst 2200 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 2200 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst 2200 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2200 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076404 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076404 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst 0.103182 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.103182 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.103182 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75522.058824 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69362 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69362 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69362 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 72129.955947 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 72129.955947 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7131000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7131000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5119000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5119000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5119000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12250000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12250000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12250000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.tags.occ_percent::total 0.007134 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
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system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=hello
cwd=
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egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
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max_stack_size=67108864
output=cout
pid=100
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=hello
cwd=
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egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
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max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 18733500 # Number of ticks simulated
final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 81438 # Simulator instruction rate (inst/s)
-host_op_rate 81405 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 589715743 # Simulator tick rate (ticks/s)
-host_mem_usage 292180 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 33056 # Simulator instruction rate (inst/s)
+host_op_rate 33048 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 239448729 # Simulator tick rate (ticks/s)
+host_mem_usage 278492 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 2585 # Number of instructions simulated
sim_ops 2585 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 19712 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 14272 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
system.physmem.bytes_read::total 19712 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 14272 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 14272 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 308 # Number of read requests responded to by this memory
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+system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1052232631 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu.data 290388876 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1052232631 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 761843756 # Instruction read bandwidth from this memory (bytes/s)
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+system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15398500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11864500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3534000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1718250 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1718250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1718250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17116750 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11864500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5252250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 17116750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17116750 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11864500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5252250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 17116750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.932384 # average ReadReq mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60931.034483 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63638.888889 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63638.888889 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
sim_ticks 27981000 # Number of ticks simulated
final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 95550 # Simulator instruction rate (inst/s)
-host_op_rate 111835 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 580422337 # Simulator tick rate (ticks/s)
-host_mem_usage 309164 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 40383 # Simulator instruction rate (inst/s)
+host_op_rate 47269 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 245344554 # Simulator tick rate (ticks/s)
+host_mem_usage 297404 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 4604 # Number of instructions simulated
sim_ops 5390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 26944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory
system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 421 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory
system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 962939137 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 697616240 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 265322898 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 962939137 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 697616240 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 265322898 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 421 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 86.669090 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 86.669090 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst 1054 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 1054 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst 846 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst 11 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst 11 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst 1900 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst 1900 # number of overall hits
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system.cpu.dcache.overall_hits::total 1900 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst 115 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst 67 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst 182 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses
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system.cpu.dcache.overall_misses::total 182 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6708741 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles
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+system.cpu.dcache.overall_miss_latency::cpu.data 11285241 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 11 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst 2082 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst 2082 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.098375 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 58336.878261 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58336.878261 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68305.970149 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68305.970149 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 62006.818681 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 36 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 36 # number of overall MSHR hits
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system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088109 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088109 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses
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addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
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eventq_index=0
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hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=20
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
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max_stack_size=67108864
output=cout
pid=100
addr_ranges=0:18446744073709551615
assoc=4
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assoc=1
clk_domain=system.cpu_clk_domain
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eventq_index=0
forward_snoops=true
hit_latency=2
type=LiveProcess
cmd=test_atomic 4
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
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max_stack_size=67108864
output=cout
pid=100
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assoc=1
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device_bus_width=8
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devices_per_rank=8
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projects / gem5.git / commitdiff