add JTAG to minimum set

diff --git a/180nm_Oct2020.mdwn b/180nm_Oct2020.mdwn
index b1a8b3ccd252783e651ce955983556f9068fd736..89002eec75fd4111778c8ef21557aab7b35df8f8 100644 (file)
--- a/180nm_Oct2020.mdwn
+++ b/180nm_Oct2020.mdwn
@@ -20,9 +20,9 @@ To be expanded with links to bugreports
 * a very very basic Common Data Bus infrastructure.
 * a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC)
 * neither in some ways is a L1 cache
-* [[180nm_Oct2020/interfaces]] we need as a bare minimum include GPIO, EINT, SPI and QSPI,
-  I2C, UART16550, LPC (from Raptor Engineering) and that actually might
-  even be it.
+* [[180nm_Oct2020/interfaces]] we need as a bare minimum include JTAG,
+  GPIO, EINT, SPI and QSPI, I2C, UART16550, LPC (from Raptor Engineering)
+  and that actually might even be it.
 
 ## Secondary priorities
 

diff --git a/180nm_Oct2020/interfaces.mdwn b/180nm_Oct2020/interfaces.mdwn
index eda03f0608784bb3c13d3e4ee6c3ee9ef6490e17..685e3bdeb770ee55934b5e4f4348090f77ec087c 100644 (file)
--- a/180nm_Oct2020/interfaces.mdwn
+++ b/180nm_Oct2020/interfaces.mdwn
@@ -11,6 +11,7 @@ These are bare minimum viability:
 * [[shakti/m_class/QSPI]]
 * [[shakti/m_class/LPC]]
 * [[shakti/m_class/EINT]]
+* [[shakti/m_class/JTAG]]
 
 Under consideration: