genlib/fifo: disable retiming on Gray counter outputs

diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
index 9f88ab5e3a17d1b269de31b17c2ba9b45738d4e1..c0e1e107444c51e8cccc83efa2f0a4a70b1054de 100644 (file)
--- a/migen/genlib/fifo.py
+++ b/migen/genlib/fifo.py
@@ -1,7 +1,7 @@
 from migen.fhdl.structure import *
 from migen.fhdl.specials import Memory
 from migen.fhdl.module import Module
-from migen.genlib.cdc import MultiReg, GrayCounter
+from migen.genlib.cdc import NoRetiming, MultiReg, GrayCounter
 
 def _inc(signal, modulo):
        if modulo == 2**len(signal):
@@ -85,12 +85,16 @@ class AsyncFIFO(Module, _FIFOInterface):
                        consume.ce.eq(self.readable & self.re)
                ]
 
-               # TODO: disable retiming on produce.q and consume.q
-
                produce_rdomain = Signal(depth_bits+1)
-               self.specials += MultiReg(produce.q, produce_rdomain, "read")
+               self.specials += [
+                       NoRetiming(produce.q),
+                       MultiReg(produce.q, produce_rdomain, "read")
+               ]
                consume_wdomain = Signal(depth_bits+1)
-               self.specials += MultiReg(consume.q, consume_wdomain, "write")
+               self.specials += [
+                       NoRetiming(consume.q),
+                       MultiReg(consume.q, consume_wdomain, "write")
+               ]
                self.comb += [
                        self.writable.eq((produce.q[-1] == consume_wdomain[-1])
                         | (produce.q[-2] == consume_wdomain[-2])