bool opt_cmod_propagation();
bool opt_zero_samples();
void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
- uint32_t spill_offset, int count);
+ uint32_t spill_offset, unsigned count);
void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
- uint32_t spill_offset, int count);
+ uint32_t spill_offset, unsigned count);
void emit_nir_code();
void nir_setup_inputs();
void
fs_visitor::emit_unspill(bblock_t *block, fs_inst *inst, fs_reg dst,
- uint32_t spill_offset, int count)
+ uint32_t spill_offset, unsigned count)
{
- int reg_size = 1;
+ unsigned reg_size = 1;
if (dispatch_width == 16 && count % 2 == 0)
reg_size = 2;
.group(reg_size * 8, 0)
.at(block, inst);
- for (int i = 0; i < count / reg_size; i++) {
+ for (unsigned i = 0; i < count / reg_size; i++) {
/* The Gen7 descriptor-based offset is 12 bits of HWORD units. Because
* the Gen7-style scratch block read is hardwired to BTI 255, on Gen9+
* it would cause the DC to do an IA-coherent read, what largely
void
fs_visitor::emit_spill(bblock_t *block, fs_inst *inst, fs_reg src,
- uint32_t spill_offset, int count)
+ uint32_t spill_offset, unsigned count)
{
- int reg_size = 1;
+ unsigned reg_size = 1;
if (dispatch_width == 16 && count % 2 == 0)
reg_size = 2;
.group(reg_size * 8, 0)
.at(block, inst->next);
- for (int i = 0; i < count / reg_size; i++) {
+ for (unsigned i = 0; i < count / reg_size; i++) {
fs_inst *spill_inst =
ibld.emit(SHADER_OPCODE_GEN4_SCRATCH_WRITE, ibld.null_reg_f(), src);
src.reg_offset += reg_size;