More realistic parameters

--HG--
extra : convert_revision : aaa4ea2b7c97df3d6b731e9252984b45715e9d6f

diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index 9fd943aaa75f886d7b7e2bf67e9cce31f024ac52..c28ffab1075dc8c62cc93f497d9fe5a755977892 100644 (file)
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -82,8 +82,7 @@ cpus = [ MemTest(atomic=not options.timing, max_loads=options.maxloads,
 
 # system simulated
 system = System(cpu = cpus, funcmem = PhysicalMemory(),
-                physmem = PhysicalMemory(latency = "50ps"),
-                membus = Bus(clock="500MHz", width=16))
+                physmem = PhysicalMemory(latency = "50ns"), membus = Bus(clock="500MHz", width=16))
 
 # l2cache & bus
 if options.caches:

diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index 4b98f6b304065afa97a43a13c60e6c130ff46251..32f3f0174af6c590f18232df9c124afdfc3c6a4a 100644 (file)
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -27,6 +27,7 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
+from m5.proxy import Self
 from MemObject import MemObject
 
 class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
@@ -77,7 +78,7 @@ class BaseCache(MemObject):
          "Squash prefetches with a later time on a subsequent miss")
     prefetch_degree = Param.Int(1,
          "Degree of the prefetch depth")
-    prefetch_latency = Param.Tick(10,
+    prefetch_latency = Param.Latency(10 * Self.latency,
          "Latency of the prefetcher")
     prefetch_policy = Param.Prefetch('none',
          "Type of prefetcher to use")