ppc_vaddr = (Addr)tc->readIntReg(17);
timer_vaddr = (Addr)tc->readIntReg(18);
- virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency);
+ virtPort.write(ppc_vaddr, (uint32_t)SimClock::Frequency);
virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
}
* calculated it by using the PIT, RTC, etc.
*/
if (kernelSymtab->findAddress("est_cycle_freq", addr))
- virtPort.write(addr, (uint64_t)(Clock::Frequency /
+ virtPort.write(addr, (uint64_t)(SimClock::Frequency /
p->boot_cpu_frequency));
TypedBufferArg<Tru64::tbl_sysinfo> elp(bufPtr);
const int clk_hz = one_million;
- elp->si_user = htog(curTick / (Clock::Frequency / clk_hz));
+ elp->si_user = htog(curTick / (SimClock::Frequency / clk_hz));
elp->si_nice = htog(0);
elp->si_sys = htog(0);
elp->si_idle = htog(0);
* calculated it by using the PIT, RTC, etc.
*/
if (kernelSymtab->findAddress("est_cycle_freq", addr))
- virtPort.write(addr, (uint64_t)(Clock::Frequency /
+ virtPort.write(addr, (uint64_t)(SimClock::Frequency /
p->boot_cpu_frequency));
/**
int cpuId() { return _cpuId; }
// Tick currentTick;
- inline Tick frequency() const { return Clock::Frequency / clock; }
+ inline Tick frequency() const { return SimClock::Frequency / clock; }
inline Tick ticks(int numCycles) const { return clock * numCycles; }
inline Tick curCycle() const { return curTick / clock; }
inline Tick tickToCycles(Tick val) const { return val / clock; }
Tick
TsunamiIO::frequency() const
{
- return Clock::Frequency / params()->frequency;
+ return SimClock::Frequency / params()->frequency;
}
Tick
EtherDump::dumpPacket(EthPacketPtr &packet)
{
pcap_pkthdr pkthdr;
- pkthdr.seconds = curTick / Clock::Int::s;
- pkthdr.microseconds = (curTick / Clock::Int::us) % ULL(1000000);
+ pkthdr.seconds = curTick / SimClock::Int::s;
+ pkthdr.microseconds = (curTick / SimClock::Int::us) % ULL(1000000);
pkthdr.caplen = std::min(packet->length, maxlen);
pkthdr.len = packet->length;
stream->write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));
regs.icr = regs.icr() | t;
- Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval();
+ Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval();
DPRINTF(EthernetIntr,
"EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
curTick, regs.itr.interval(), itr_interval);
DPRINTF(Ethernet,
"Possibly scheduling interrupt because of imr write\n");
if (!interEvent.scheduled()) {
- Tick t = curTick + Clock::Int::ns * 256 * regs.itr.interval();
+ Tick t = curTick + SimClock::Int::ns * 256 * regs.itr.interval();
DPRINTF(Ethernet, "Scheduling for %d\n", t);
schedule(interEvent, t);
}
*/
void cpuClearInt();
- Tick intClock() { return Clock::Int::ns * 1024; }
+ Tick intClock() { return SimClock::Int::ns * 1024; }
/** This function is used to restart the clock so it can handle things like
* draining and resume in one place. */
Intel8254Timer::Counter::CounterEvent::CounterEvent(Counter* c_ptr)
{
- interval = (Tick)(Clock::Float::s / 1193180.0);
+ interval = (Tick)(SimClock::Float::s / 1193180.0);
counter = c_ptr;
}
MC146818::RTCTickEvent::process()
{
DPRINTF(MC146818, "RTC clock tick\n");
- parent->schedule(this, curTick + Clock::Int::s);
+ parent->schedule(this, curTick + SimClock::Int::s);
parent->tickClock();
}
RTCTickEvent(MC146818 * _parent) : parent(_parent)
{
- parent->schedule(this, curTick + Clock::Int::s);
+ parent->schedule(this, curTick + SimClock::Int::s);
}
/** Event process to occur at interrupt*/
Tick
MaltaIO::frequency() const
{
- return Clock::Frequency / params()->frequency;
+ return SimClock::Frequency / params()->frequency;
}
Tick
void
Uart8250::IntrEvent::scheduleIntr()
{
- static const Tick interval = 225 * Clock::Int::ns;
+ static const Tick interval = 225 * SimClock::Int::ns;
DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
curTick + interval);
if (!scheduled())
if (UART_IER_THRI & IER)
{
DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
- if (curTick - lastTxInt > 225 * Clock::Int::ns) {
+ if (curTick - lastTxInt > 225 * SimClock::Int::ns) {
DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
curTick, lastTxInt);
txIntrEvent.process();
SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when)
{
assert(when > curTick);
- assert(when < curTick + Clock::Int::ms);
+ assert(when < curTick + SimClock::Int::ms);
// Nothing is on the list: add it and schedule an event
if (transmitList.empty() || when < transmitList.front().tick) {
Tick curTick = 0;
-namespace Clock {
+namespace SimClock {
/// The simulated frequency of curTick. (In ticks per second)
Tick Frequency;
Tick ps;
/* namespace Float */ }
-/* namespace Clock */ }
+/* namespace SimClock */ }
void
setClockFrequency(Tick ticksPerSecond)
{
- using namespace Clock;
+ using namespace SimClock;
Frequency = ticksPerSecond;
Float::s = static_cast<double>(Frequency);
Float::ms = Float::s / 1.0e3;
extern Tick curTick;
const Tick retryTime = 1000;
-namespace Clock {
+namespace SimClock {
/// The simulated frequency of curTick.
extern Tick Frequency;
extern Tick ns;
extern Tick ps;
/* namespace Int */ }
-/* namespace Clock */ }
+/* namespace SimClock */ }
void setClockFrequency(Tick ticksPerSecond);
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
- Tick resume = curTick + Clock::Int::ns * ns;
+ Tick resume = curTick + SimClock::Int::ns * ns;
mainEventQueue.reschedule(quiesceEvent, resume, true);
uint64_t
quiesceTime(ThreadContext *tc)
{
- return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns;
+ return (tc->readLastActivate() - tc->readLastSuspend()) /
+ SimClock::Int::ns;
}
#endif
uint64_t
rpns(ThreadContext *tc)
{
- return curTick / Clock::Int::ns;
+ return curTick / SimClock::Int::ns;
}
void
void
m5exit(ThreadContext *tc, Tick delay)
{
- Tick when = curTick + delay * Clock::Int::ns;
+ Tick when = curTick + delay * SimClock::Int::ns;
Event *event = new SimLoopExitEvent("m5_exit instruction encountered", 0);
mainEventQueue.schedule(event, when);
}
return;
- Tick when = curTick + delay * Clock::Int::ns;
- Tick repeat = period * Clock::Int::ns;
+ Tick when = curTick + delay * SimClock::Int::ns;
+ Tick repeat = period * SimClock::Int::ns;
Stats::StatEvent(false, true, when, repeat);
}
return;
- Tick when = curTick + delay * Clock::Int::ns;
- Tick repeat = period * Clock::Int::ns;
+ Tick when = curTick + delay * SimClock::Int::ns;
+ Tick repeat = period * SimClock::Int::ns;
Stats::StatEvent(true, false, when, repeat);
}
return;
- Tick when = curTick + delay * Clock::Int::ns;
- Tick repeat = period * Clock::Int::ns;
+ Tick when = curTick + delay * SimClock::Int::ns;
+ Tick repeat = period * SimClock::Int::ns;
Stats::StatEvent(true, true, when, repeat);
}
if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
return;
- Tick when = curTick + delay * Clock::Int::ns;
- Tick repeat = period * Clock::Int::ns;
+ Tick when = curTick + delay * SimClock::Int::ns;
+ Tick repeat = period * SimClock::Int::ns;
Event *event = new SimLoopExitEvent("checkpoint", 0, repeat);
mainEventQueue.schedule(event, when);
;
simFreq
- .scalar(Clock::Frequency)
+ .scalar(SimClock::Frequency)
.name("sim_freq")
.desc("Frequency of simulated ticks")
;
void
getElapsedTime(T1 &sec, T2 &usec)
{
- int elapsed_usecs = curTick / Clock::Int::us;
+ int elapsed_usecs = curTick / SimClock::Int::us;
sec = elapsed_usecs / one_million;
usec = elapsed_usecs % one_million;
}
TypedBufferArg<typename OS::tms> bufp(process->getSyscallArg(tc, index));
// Fill in the time structure (in clocks)
- int64_t clocks = curTick * OS::M5_SC_CLK_TCK / Clock::Int::s;
+ int64_t clocks = curTick * OS::M5_SC_CLK_TCK / SimClock::Int::s;
bufp->tms_utime = clocks;
bufp->tms_stime = 0;
bufp->tms_cutime = 0;