Fix write signal name for CSR (fixes #5)

diff --git a/gram/dfii.py b/gram/dfii.py
index 143fd27f5b3600b54c7c67d182354056ab8e34fe..f5b883f80803fe9195ce4a5b8906d7b6a04751f2 100644 (file)
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -54,7 +54,7 @@ class PhaseInjector(Elaboratable):
             ]
 
         with m.If(self._phase.rddata_valid):
-            m.d.sync += self._rddata.w_data.eq(self._phase.rddata)
+            m.d.sync += self._rddata.r_data.eq(self._phase.rddata)
 
         return m