(no commit message)

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 0c9a51211c3fa8c9df44c601942930328375909e..08d27ef02cf9e16c745ceae716190d1b9cbcbc27 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -71,7 +71,10 @@ The following modes make sense:
 
 * saturation
 * predicate-result (mostly for cache-inhibited LD/ST)
-* normal
+* simple (no augmentation)
+
+
+
 * fail-first (where Vector Indexed is banned)
 * Signed Effective Address computation (Vector Indexed only)
 * Pack/Unpack (on LD/ST immediate operations only)
@@ -105,7 +108,7 @@ The table for [[sv/svp64]] for `immed(RA)` which is `RM.MODE`
 
 | 0-1 |  2  |  3   4  |  description               |
 | --- | --- |---------|--------------------------- |
-| 00  | 0   |  zz els | normal mode                |
+| 00  | 0   |  zz els | simple mode                |
 | 00  | 1   |  zz els | Structured Pack/Unpack     |
 | 01  | inv | CR-bit  | Rc=1: ffirst CR sel        |
 | 01  | inv | els RC1 |  Rc=0: ffirst z/nonz       |
@@ -160,7 +163,7 @@ but are the same `RM.MODE` bits (19:23 of `RM`):
 
 | 0-1 |  2  |  3   4  |  description              |
 | --- | --- |---------|-------------------------- |
-| 00  | SEA |  dz  sz | normal mode        |
+| 00  | SEA |  dz  sz | simple mode        |
 | 01  | SEA | dz sz   | Strided (scalar only source)   |
 | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |