re PR target/70293 ([ICE, AVX-512] Wrong reg constraints in vec_dup)

PR target/70293

gcc/
	* config/i386 (define_insn "*vec_dup<mode>"/AVX2): Block
	third alternative for AVX-512VL target,

gcc/testsuite/
	* gcc.target/i386/pr70293.c: New test.

From-SVN: r234363

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7a918672563a7df1886a77bb62de15b842614928..02c2580193999fd46c1b0f54fa18e0ac16c751d7 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-03-21  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+       PR target/70293
+        * config/i386/sse.md: (define_insn "*vec_dup<mode>"/AVX2):
+       Block third alternative for AVX-512VL target,
+
 2016-03-21  Martin Liska  <mliska@suse.cz>
 
        PR hsa/70234

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b25c2465ebf784b92423be682eb30aef914f0dd5..44141ea5d97f92e2e067d84fd79a33ea5f90988e 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -17419,7 +17419,8 @@
    v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0|%0, %1}
    v<sseintprefix>broadcast<bcstscalarsuff>\t{%x1, %0|%0, %x1}
    #"
-  [(set_attr "type" "ssemov")
+  [(set_attr "isa" "*,*,noavx512vl")
+   (set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "maybe_evex")
    (set_attr "mode" "<sseinsnmode>")])

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index f7ca6848fd04821ad096b6e6008e74a2ec332210..9f4d811710f7e6e1cc63d8d885411566bd845b4f 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-03-21  Kirill Yukhin  <kirill.yukhin@intel.com>
+
+       PR target/70293
+       * gcc.target/i386/pr70293.c: New test.
+
 2016-03-21  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/70288

diff --git a/gcc/testsuite/gcc.target/i386/pr70293.c b/gcc/testsuite/gcc.target/i386/pr70293.c
new file mode 100644 (file)
index 0000000..4510166
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70293.c
@@ -0,0 +1,38 @@
+/* PR target/70293 */
+/* { dg-do compile } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mtune=westmere -mavx512vl -O2" } */
+
+typedef short __v8hi __attribute__((__vector_size__(16)));
+typedef int __v8hu __attribute__((__vector_size__(16)));
+typedef long __m128i __attribute__((__vector_size__(16)));
+__m128i _mm_madd_epi16___B, _mm_mullo_epi16___A,
+    scaled_bilinear_scanline_sse2_8888_8_8888_OVER_xmm_b,
+    scaled_bilinear_scanline_sse2_8888_8_8888_OVER___trans_tmp_16,
+    scaled_bilinear_scanline_sse2_8888_8_8888_OVER___trans_tmp_13;
+int _mm_srli_epi16___B, scaled_bilinear_scanline_sse2_8888_8_8888_OVER_m,
+    scaled_bilinear_scanline_sse2_8888_8_8888_OVER_dst,
+    scaled_bilinear_scanline_sse2_8888_8_8888_OVER_wt;
+__m128i _mm_set_epi16();
+void _mm_cvtsi128_si32();
+void
+scaled_bilinear_scanline_sse2_8888_8_8888_OVER(int p1) {
+  __m128i __trans_tmp_12, __trans_tmp_6, __trans_tmp_5, xmm_x = _mm_set_epi16();
+  int mask;
+  __trans_tmp_5 = (__m128i){scaled_bilinear_scanline_sse2_8888_8_8888_OVER_wt};
+  __trans_tmp_6 = (__m128i)(__v8hi){p1, p1, p1, p1, p1, p1, p1, p1};
+  while (scaled_bilinear_scanline_sse2_8888_8_8888_OVER_dst) {
+    scaled_bilinear_scanline_sse2_8888_8_8888_OVER_m = mask++;
+    if (scaled_bilinear_scanline_sse2_8888_8_8888_OVER_m) {
+      __trans_tmp_12 =
+          (__m128i)((__v8hu)_mm_mullo_epi16___A * (__v8hu)__trans_tmp_6);
+      scaled_bilinear_scanline_sse2_8888_8_8888_OVER_xmm_b = __trans_tmp_12;
+      scaled_bilinear_scanline_sse2_8888_8_8888_OVER___trans_tmp_13 =
+          (__m128i)__builtin_ia32_psrlwi128((__v8hi)xmm_x, _mm_srli_epi16___B);
+      scaled_bilinear_scanline_sse2_8888_8_8888_OVER___trans_tmp_16 =
+          (__m128i)__builtin_ia32_pmaddwd128((__v8hi)__trans_tmp_5,
+                                             (__v8hi)_mm_madd_epi16___B);
+      _mm_cvtsi128_si32();
+    }
+  }
+}