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diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 99b33f7de373e7059563dc68fa0caa0d9db0e9c9..cb2ab9d8912f48172dc8f5adedbe9450057515fb 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -511,7 +511,9 @@ The register files are therefore extended:
 
 In the following tables register numbers are constructed from the
 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
-or EXTRA3 field from the SV Prefix.  The prefixing is arranged so that
+or EXTRA3 field from the SV Prefix, determined by the specific
+RM-xx-yyyy designation for a given instruction.
+The prefixing is arranged so that
 interoperability between prefixing and nonprefixing of scalar registers
 is direct and convenient (when the EXTRA field is all zeros).
 
@@ -529,13 +531,13 @@ A pseudocode algorithm explains the relationship, for INT/FP (see [[svp64/append
 Future versions may extend to 256 by shifting Vector numbering up.
 Scalar will not be altered.
 
+Note that in some cases the range of starting points for Vectors
+is limited. 
+
 ## INT/FP EXTRA3
 
-alternative which is understandable and, if EXTRA3 is zero, maps to
-"no effect" (scalar OpenPOWER ISA field naming).  also, these are the
-encodings used in the original SV Prefix scheme.  the reason why they
-were chosen is so that scalar registers in v3.0B and prefixed scalar
-registers have access to the same 32 registers.
+If EXTRA3 is zero, maps to
+"scalar identity" (scalar OpenPOWER ISA field naming).
 
 Fields are as follows:
 
@@ -561,8 +563,8 @@ Fields are as follows:
 
 ## INT/FP EXTRA2
 
-alternative which is understandable and, if EXTRA2 is zero will map to
-"no effect" i.e Scalar OpenPOWER register naming:
+If EXTRA2 is zero will map to
+"scalar identity behaviour" i.e Scalar OpenPOWER register naming:
 
 | Value | Mode | Range/inc | 6..0 |
 |-----------|-------|---------------|-----------|
@@ -574,6 +576,7 @@ alternative which is understandable and, if EXTRA2 is zero will map to
 ## CR Field EXTRA3
 
 CR Field encoding is essentially the same but made more complex due to CRs being bit-based.  See [[svp64/appendix]] for explanation and pseudocode.
+Note that Vectors may only start from CR0, CR4, CR8, CR12, CR16...
 
 Encoding shown MSB down to LSB
 
@@ -606,6 +609,8 @@ For a 3-bit operand (e.g. BFA):
 ## CR EXTRA2
 
 CR encoding is essentially the same but made more complex due to CRs being bit-based.  See separate section for explanation and pseudocode.
+Note that Vectors may only start from CR0, CR8, CR16, CR24, CR32...
+
 
 Encoding shown MSB down to LSB