sim: Make the drain state a global typed enum

The drain state enum is currently a part of the Drainable
interface. The same state machine will be used by the DrainManager to
identify the global state of the simulator. Make the drain state a
global typed enum to better cater for this usage scenario.

diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index f58d8a2680cb6cfe0c4146ea3c4552dd711ca8b7..297054131e2b025d71fac6e21dd54faecc607fff 100644 (file)
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -139,7 +139,7 @@ TableWalker::completeDrain()
 {
     if (drainManager && stateQueues[L1].empty() && stateQueues[L2].empty() &&
         pendingQueue.empty()) {
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
         DPRINTF(Drain, "TableWalker done draining, processing drain event\n");
         drainManager->signalDrainDone();
         drainManager = NULL;
@@ -160,13 +160,13 @@ TableWalker::drain(DrainManager *dm)
 
     if (state_queues_not_empty || pendingQueue.size()) {
         drainManager = dm;
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
         DPRINTF(Drain, "TableWalker not drained\n");
 
         // return port drain count plus the table walker itself needs to drain
         return 1;
     } else {
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
         DPRINTF(Drain, "TableWalker free, no need to drain\n");
 
         // table walker is drained, but its ports may still need to be drained

diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index d21bf7042d356fa64f302238618fde04ba1c41e2..ac1a18bf978a1fec1ac7f82cce9c9a1877e27e86 100644 (file)
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -217,7 +217,7 @@ void
 MinorCPU::signalDrainDone()
 {
     DPRINTF(Drain, "MinorCPU drain done\n");
-    setDrainState(Drainable::Drained);
+    setDrainState(DrainState::Drained);
     drainManager->signalDrainDone();
     drainManager = NULL;
 }
@@ -225,8 +225,8 @@ MinorCPU::signalDrainDone()
 void
 MinorCPU::drainResume()
 {
-    assert(getDrainState() == Drainable::Drained ||
-        getDrainState() == Drainable::Running);
+    assert(getDrainState() == DrainState::Drained ||
+        getDrainState() == DrainState::Running);
 
     if (switchedOut()) {
         DPRINTF(Drain, "drainResume while switched out.  Ignoring\n");
@@ -243,7 +243,7 @@ MinorCPU::drainResume()
     wakeup();
     pipeline->drainResume();
 
-    setDrainState(Drainable::Running);
+    setDrainState(DrainState::Running);
 }
 
 void

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 18e9582784e48e8b6c277981392f166000da73d4..89256a7f080f168c38e197c32bbe94d1ba47f645 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -539,7 +539,7 @@ FullO3CPU<Impl>::tick()
 {
     DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n");
     assert(!switchedOut());
-    assert(getDrainState() != Drainable::Drained);
+    assert(getDrainState() != DrainState::Drained);
 
     ++numCycles;
     ppCycles->notify(1);
@@ -712,7 +712,7 @@ FullO3CPU<Impl>::activateContext(ThreadID tid)
     // We don't want to wake the CPU if it is drained. In that case,
     // we just want to flag the thread as active and schedule the tick
     // event from drainResume() instead.
-    if (getDrainState() == Drainable::Drained)
+    if (getDrainState() == DrainState::Drained)
         return;
 
     // If we are time 0 or if the last activation time is in the past,
@@ -1004,12 +1004,12 @@ FullO3CPU<Impl>::drain(DrainManager *drain_manager)
 {
     // If the CPU isn't doing anything, then return immediately.
     if (switchedOut()) {
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
         return 0;
     }
 
     DPRINTF(Drain, "Draining...\n");
-    setDrainState(Drainable::Draining);
+    setDrainState(DrainState::Draining);
 
     // We only need to signal a drain to the commit stage as this
     // initiates squashing controls the draining. Once the commit
@@ -1031,7 +1031,7 @@ FullO3CPU<Impl>::drain(DrainManager *drain_manager)
 
         return 1;
     } else {
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
         DPRINTF(Drain, "CPU is already drained\n");
         if (tickEvent.scheduled())
             deschedule(tickEvent);
@@ -1132,7 +1132,7 @@ template <class Impl>
 void
 FullO3CPU<Impl>::drainResume()
 {
-    setDrainState(Drainable::Running);
+    setDrainState(DrainState::Running);
     if (switchedOut())
         return;
 

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index bbc9fde8e3011d1830e95e27379a0b7014b53e9c..44400542a3b8fab6339b96a74aed8dbf225fd679 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -336,7 +336,7 @@ class FullO3CPU : public BaseO3CPU
     void updateThreadPriority();
 
     /** Is the CPU draining? */
-    bool isDraining() const { return getDrainState() == Drainable::Draining; }
+    bool isDraining() const { return getDrainState() == DrainState::Draining; }
 
     void serializeThread(CheckpointOut &cp,
                          ThreadID tid) const M5_ATTR_OVERRIDE;

diff --git a/src/dev/arm/flash_device.cc b/src/dev/arm/flash_device.cc
index 96f8f05668d94c84685c5e43d8bd4aa0dbf87df8..e4bfcf5c96cefae5a4b5490a2745af61fae15d73 100644 (file)
--- a/src/dev/arm/flash_device.cc
+++ b/src/dev/arm/flash_device.cc
@@ -601,10 +601,10 @@ FlashDevice::drain(DrainManager *dm)
 
     if (count) {
         DPRINTF(Drain, "Flash device is draining...\n");
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
     } else {
         DPRINTF(Drain, "Flash device drained\n");
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
     }
     return count;
 }

diff --git a/src/dev/arm/ufs_device.cc b/src/dev/arm/ufs_device.cc
index 02df00e351a8757238b34b4e17cf709e3cbe151c..ef639821615612fbbb232817d21c07ca6e65a45a 100644 (file)
--- a/src/dev/arm/ufs_device.cc
+++ b/src/dev/arm/ufs_device.cc
@@ -2333,10 +2333,10 @@ UFSHostDevice::drain(DrainManager *dm)
 
     if (count) {
         DPRINTF(UFSHostDevice, "UFSDevice is draining...\n");
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
     } else {
         DPRINTF(UFSHostDevice, "UFSDevice drained\n");
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
     }
     return count;
 }

diff --git a/src/dev/copy_engine.cc b/src/dev/copy_engine.cc
index 5506103b1a5969c6f9f610c77a75c5584522b977..035f824fa4e56b1d5f810168c426154d44841582 100644 (file)
--- a/src/dev/copy_engine.cc
+++ b/src/dev/copy_engine.cc
@@ -140,12 +140,12 @@ CopyEngine::CopyEngineChannel::recvCommand()
         cr.status.dma_transfer_status(0);
         nextState = DescriptorFetch;
         fetchAddress = cr.descChainAddr;
-        if (ce->getDrainState() == Drainable::Running)
+        if (ce->getDrainState() == DrainState::Running)
             fetchDescriptor(cr.descChainAddr);
     } else if (cr.command.append_dma()) {
         if (!busy) {
             nextState = AddressFetch;
-            if (ce->getDrainState() == Drainable::Running)
+            if (ce->getDrainState() == DrainState::Running)
                 fetchNextAddr(lastDescriptorAddr);
         } else
             refreshNext = true;
@@ -635,20 +635,20 @@ CopyEngine::CopyEngineChannel::fetchAddrComplete()
 bool
 CopyEngine::CopyEngineChannel::inDrain()
 {
-    if (ce->getDrainState() == Drainable::Draining) {
+    if (ce->getDrainState() == DrainState::Draining) {
         DPRINTF(Drain, "CopyEngine done draining, processing drain event\n");
         assert(drainManager);
         drainManager->signalDrainDone();
         drainManager = NULL;
     }
 
-    return ce->getDrainState() != Drainable::Running;
+    return ce->getDrainState() != DrainState::Running;
 }
 
 unsigned int
 CopyEngine::CopyEngineChannel::drain(DrainManager *dm)
 {
-    if (nextState == Idle || ce->getDrainState() != Drainable::Running)
+    if (nextState == Idle || ce->getDrainState() != DrainState::Running)
         return 0;
     unsigned int count = 1;
     count += cePort.drain(dm);
@@ -667,9 +667,9 @@ CopyEngine::drain(DrainManager *dm)
         count += chan[x]->drain(dm);
 
     if (count)
-        setDrainState(Draining);
+        setDrainState(DrainState::Draining);
     else
-        setDrainState(Drained);
+        setDrainState(DrainState::Drained);
 
     DPRINTF(Drain, "CopyEngine not drained\n");
     return count;

diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 24d833b54706272564667b11652848fdcf5fbca2..a778833ffa67786187e7d737aa6b92546b968edb 100644 (file)
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -130,9 +130,9 @@ DmaDevice::drain(DrainManager *dm)
 {
     unsigned int count = pioPort.drain(dm) + dmaPort.drain(dm);
     if (count)
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
     else
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
     return count;
 }
 

diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index 0ff52bda064e8065248d3ade46778611dce9bebc..3b49c8b5d3fa61ca429fe4a538984b42f03b8381 100644 (file)
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -586,7 +586,7 @@ IGbE::write(PacketPtr pkt)
       case REG_RDT:
         regs.rdt = val;
         DPRINTF(EthernetSM, "RXS: RDT Updated.\n");
-        if (getDrainState() == Drainable::Running) {
+        if (getDrainState() == DrainState::Running) {
             DPRINTF(EthernetSM, "RXS: RDT Fetching Descriptors!\n");
             rxDescCache.fetchDescriptors();
         } else {
@@ -626,7 +626,7 @@ IGbE::write(PacketPtr pkt)
       case REG_TDT:
         regs.tdt = val;
         DPRINTF(EthernetSM, "TXS: TX Tail pointer updated\n");
-        if (getDrainState() == Drainable::Running) {
+        if (getDrainState() == DrainState::Running) {
             DPRINTF(EthernetSM, "TXS: TDT Fetching Descriptors!\n");
             txDescCache.fetchDescriptors();
         } else {
@@ -905,7 +905,7 @@ void
 IGbE::DescCache<T>::writeback1()
 {
     // If we're draining delay issuing this DMA
-    if (igbe->getDrainState() != Drainable::Running) {
+    if (igbe->getDrainState() != DrainState::Running) {
         igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
         return;
     }
@@ -986,7 +986,7 @@ void
 IGbE::DescCache<T>::fetchDescriptors1()
 {
     // If we're draining delay issuing this DMA
-    if (igbe->getDrainState() != Drainable::Running) {
+    if (igbe->getDrainState() != DrainState::Running) {
         igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
         return;
     }
@@ -2051,7 +2051,7 @@ void
 IGbE::restartClock()
 {
     if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
-        getDrainState() == Drainable::Running)
+        getDrainState() == DrainState::Running)
         schedule(tickEvent, clockEdge(Cycles(1)));
 }
 
@@ -2075,9 +2075,9 @@ IGbE::drain(DrainManager *dm)
 
     if (count) {
         DPRINTF(Drain, "IGbE not drained\n");
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
     } else
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
 
     return count;
 }

diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh
index d353c1d8349fb0e264556aaa7bdb8f2639572345..116fa5b95308f8ece2b905f5750bccf3c0fe3943 100644 (file)
--- a/src/dev/i8254xGBe.hh
+++ b/src/dev/i8254xGBe.hh
@@ -352,7 +352,7 @@ class IGbE : public EtherDevice
         virtual void updateHead(long h) { igbe->regs.rdh(h); }
         virtual void enableSm();
         virtual void fetchAfterWb() {
-            if (!igbe->rxTick && igbe->getDrainState() == Drainable::Running)
+            if (!igbe->rxTick && igbe->getDrainState() == DrainState::Running)
                 fetchDescriptors();
         }
 
@@ -414,7 +414,7 @@ class IGbE : public EtherDevice
         virtual void enableSm();
         virtual void actionAfterWb();
         virtual void fetchAfterWb() {
-            if (!igbe->txTick && igbe->getDrainState() == Drainable::Running)
+            if (!igbe->txTick && igbe->getDrainState() == DrainState::Running)
                 fetchDescriptors();
         }
         

diff --git a/src/dev/ide_disk.cc b/src/dev/ide_disk.cc
index bbdee8e512c1f5ee233c5cb20e6bf877357df2eb..2e6df380584a5b73aac474e74090dd9fd956d977 100644 (file)
--- a/src/dev/ide_disk.cc
+++ b/src/dev/ide_disk.cc
@@ -342,7 +342,7 @@ IdeDisk::doDmaTransfer()
         panic("Inconsistent DMA transfer state: dmaState = %d devState = %d\n",
               dmaState, devState);
 
-    if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
+    if (ctrl->dmaPending() || ctrl->getDrainState() != DrainState::Running) {
         schedule(dmaTransferEvent, curTick() + DMA_BACKOFF_PERIOD);
         return;
     } else
@@ -436,7 +436,7 @@ IdeDisk::doDmaRead()
                 curPrd.getByteCount(), TheISA::PageBytes);
 
     }
-    if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
+    if (ctrl->dmaPending() || ctrl->getDrainState() != DrainState::Running) {
         schedule(dmaReadWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
         return;
     } else if (!dmaReadCG->done()) {
@@ -518,7 +518,7 @@ IdeDisk::doDmaWrite()
         dmaWriteCG = new ChunkGenerator(curPrd.getBaseAddr(),
                 curPrd.getByteCount(), TheISA::PageBytes);
     }
-    if (ctrl->dmaPending() || ctrl->getDrainState() != Drainable::Running) {
+    if (ctrl->dmaPending() || ctrl->getDrainState() != DrainState::Running) {
         schedule(dmaWriteWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
         DPRINTF(IdeDisk, "doDmaWrite: rescheduling\n");
         return;

diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index c25a28dd2f7ec6d7f268c733cc304e368856de98..9e5855a0b77d043e4cd5db56e587c878293a5b1c 100644 (file)
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -99,9 +99,9 @@ PioDevice::drain(DrainManager *dm)
     unsigned int count;
     count = pioPort.drain(dm);
     if (count)
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
     else
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
     return count;
 }
 

diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index c525f6359e0186504531ab6cb69c773bcce02531..7a8d202c5482f4ccc3d961d15e4ba40daf29a7c5 100644 (file)
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -1068,7 +1068,7 @@ NSGigE::doRxDmaRead()
     assert(rxDmaState == dmaIdle || rxDmaState == dmaReadWaiting);
     rxDmaState = dmaReading;
 
-    if (dmaPending() || getDrainState() != Drainable::Running)
+    if (dmaPending() || getDrainState() != DrainState::Running)
         rxDmaState = dmaReadWaiting;
     else
         dmaRead(rxDmaAddr, rxDmaLen, &rxDmaReadEvent, (uint8_t*)rxDmaData);
@@ -1099,7 +1099,7 @@ NSGigE::doRxDmaWrite()
     assert(rxDmaState == dmaIdle || rxDmaState == dmaWriteWaiting);
     rxDmaState = dmaWriting;
 
-    if (dmaPending() || getDrainState() != Running)
+    if (dmaPending() || getDrainState() != DrainState::Running)
         rxDmaState = dmaWriteWaiting;
     else
         dmaWrite(rxDmaAddr, rxDmaLen, &rxDmaWriteEvent, (uint8_t*)rxDmaData);
@@ -1515,7 +1515,7 @@ NSGigE::doTxDmaRead()
     assert(txDmaState == dmaIdle || txDmaState == dmaReadWaiting);
     txDmaState = dmaReading;
 
-    if (dmaPending() || getDrainState() != Running)
+    if (dmaPending() || getDrainState() != DrainState::Running)
         txDmaState = dmaReadWaiting;
     else
         dmaRead(txDmaAddr, txDmaLen, &txDmaReadEvent, (uint8_t*)txDmaData);
@@ -1546,7 +1546,7 @@ NSGigE::doTxDmaWrite()
     assert(txDmaState == dmaIdle || txDmaState == dmaWriteWaiting);
     txDmaState = dmaWriting;
 
-    if (dmaPending() || getDrainState() != Running)
+    if (dmaPending() || getDrainState() != DrainState::Running)
         txDmaState = dmaWriteWaiting;
     else
         dmaWrite(txDmaAddr, txDmaLen, &txDmaWriteEvent, (uint8_t*)txDmaData);

diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index 581ae2ebd7dd680b078f0b87a7e867f17d3ce382..5788c94d277dce68b4ac1abe4510dc1d8a412e49 100644 (file)
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -261,9 +261,9 @@ PciDevice::drain(DrainManager *dm)
     unsigned int count;
     count = pioPort.drain(dm) + dmaPort.drain(dm) + configPort.drain(dm);
     if (count)
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
     else
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
     return count;
 }
 

diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index d5a05b3198137101e663544b7bffb66cc8fa2559..1ba0762006347546154dd8ff5d3e93baac5c0ce6 100644 (file)
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -868,7 +868,7 @@ Device::rxKick()
         break;
 
       case rxBeginCopy:
-        if (dmaPending() || getDrainState() != Drainable::Running)
+        if (dmaPending() || getDrainState() != DrainState::Running)
             goto exit;
 
         rxDmaAddr = params()->platform->pciToDma(
@@ -1068,7 +1068,7 @@ Device::txKick()
         break;
 
       case txBeginCopy:
-        if (dmaPending() || getDrainState() != Drainable::Running)
+        if (dmaPending() || getDrainState() != DrainState::Running)
             goto exit;
 
         txDmaAddr = params()->platform->pciToDma(

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 1d0b9a3dd86bc30aed6a83d7742e8f3bc644c333..e58d5f6b977d96869d5143cc6bbde06b76343208 100644 (file)
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -783,12 +783,12 @@ BaseCache::drain(DrainManager *dm)
 
     // Set status
     if (count != 0) {
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
         DPRINTF(Drain, "Cache not drained\n");
         return count;
     }
 
-    setDrainState(Drainable::Drained);
+    setDrainState(DrainState::Drained);
     return 0;
 }
 

diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index f8587e1f17263897b6208948632d34d764082f5f..3736c9f21760709e9602c2c5a4e4b308cf836f38 100644 (file)
--- a/src/mem/cache/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
@@ -186,7 +186,7 @@ MSHRQueue::deallocateOne(MSHR *mshr)
         DPRINTF(Drain, "MSHRQueue now empty, signalling drained\n");
         drainManager->signalDrainDone();
         drainManager = NULL;
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
     }
     return retval;
 }
@@ -269,11 +269,11 @@ unsigned int
 MSHRQueue::drain(DrainManager *dm)
 {
     if (allocated == 0) {
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
         return 0;
     } else {
         drainManager = dm;
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
         return 1;
     }
 }

diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 7657cc7767e83e7cb5af0a7da922869d84c50787..9d264d9717a0c2185a8dd00622cca2328fc474e5 100644 (file)
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -2189,9 +2189,9 @@ DRAMCtrl::drain(DrainManager *dm)
     }
 
     if (count)
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
     else
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
     return count;
 }
 

diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc
index be244bd4a3364dbe2644e6625c6965803956510b..dfeca0d47997394f2476c0fe6fa31101ba943491 100644 (file)
--- a/src/mem/dramsim2.cc
+++ b/src/mem/dramsim2.cc
@@ -362,11 +362,11 @@ DRAMSim2::drain(DrainManager* dm)
     // check our outstanding reads and writes and if any they need to
     // drain
     if (nbrOutstanding() != 0) {
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
         drainManager = dm;
         return 1;
     } else {
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
         return 0;
     }
 }

diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 43ef37f08e85cc6ffa9baa46e44b999cafe8b4d4..b105380246eaa627570945abd137e3f49844d91e 100644 (file)
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -192,12 +192,12 @@ DMASequencer::drain(DrainManager *dm)
         drainManager = dm;
 
         DPRINTF(Drain, "DMASequencer not drained\n");
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
         return child_drain_count + 1;
     }
 
     drainManager = NULL;
-    setDrainState(Drainable::Drained);
+    setDrainState(DrainState::Drained);
     return child_drain_count;
 }
 

diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index ec1780c7a94695f2a56e865fd55e0e683c1c55de..b6aa871b3815a30167201057a40764b8aa7d8ae8 100644 (file)
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -449,12 +449,12 @@ RubyPort::drain(DrainManager *dm)
         drainManager = dm;
 
         DPRINTF(Drain, "RubyPort not drained\n");
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
         return child_drain_count + 1;
     }
 
     drainManager = NULL;
-    setDrainState(Drainable::Drained);
+    setDrainState(DrainState::Drained);
     return child_drain_count;
 }
 

diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index b1d22b549a084f35627b244a3264fa53e32fb963..c33f5f819a93cb5a89441f4c39761fc95f947f66 100644 (file)
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -77,7 +77,7 @@ Sequencer::~Sequencer()
 void
 Sequencer::wakeup()
 {
-    assert(getDrainState() != Drainable::Draining);
+    assert(getDrainState() != DrainState::Draining);
 
     // Check for deadlock of any of the requests
     Cycles current_time = curCycle();
@@ -215,7 +215,7 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
 
     // See if we should schedule a deadlock check
     if (!deadlockCheckEvent.scheduled() &&
-        getDrainState() != Drainable::Draining) {
+        getDrainState() != DrainState::Draining) {
         schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
     }
 

diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index 1803394594d761ea28d64577ee2afbad0351f710..f363018095b35c20b5ba7e775a379569b3c078e2 100644 (file)
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -246,9 +246,9 @@ SimpleMemory::drain(DrainManager *dm)
      }
 
     if (count)
-        setDrainState(Drainable::Draining);
+        setDrainState(DrainState::Draining);
     else
-        setDrainState(Drainable::Drained);
+        setDrainState(DrainState::Drained);
     return count;
 }
 

diff --git a/src/sim/drain.cc b/src/sim/drain.cc
index 3daf762f66657b53163049ebd69a573036b8d9c7..90fb0c18dc331f99e3c05999965634bf7f051d67 100644 (file)
--- a/src/sim/drain.cc
+++ b/src/sim/drain.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2015 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -58,7 +58,7 @@ DrainManager::drainCycleDone()
 
 
 Drainable::Drainable()
-    : _drainState(Running)
+    : _drainState(DrainState::Running)
 {
 }
 
@@ -69,5 +69,5 @@ Drainable::~Drainable()
 void
 Drainable::drainResume()
 {
-    _drainState = Running;
+    _drainState = DrainState::Running;
 }

diff --git a/src/sim/drain.hh b/src/sim/drain.hh
index 6f0769f34387a57d86f078315b4c5de710b93df9..ae80fb7e93a1ca0c5e3f76040e0fa903026bbd2e 100644 (file)
--- a/src/sim/drain.hh
+++ b/src/sim/drain.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2015 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -45,7 +45,33 @@
 
 #include "base/flags.hh"
 
-class Event;
+class Drainable;
+
+#ifndef SWIG // SWIG doesn't support strongly typed enums
+/**
+ * Object drain/handover states
+ *
+ * An object starts out in the Running state. When the simulator
+ * prepares to take a snapshot or prepares a CPU for handover, it
+ * calls the drain() method to transfer the object into the Draining
+ * or Drained state. If any object enters the Draining state
+ * (Drainable::drain() returning >0), simulation continues until it
+ * all objects have entered the Drained state.
+ *
+ * Before resuming simulation, the simulator calls resume() to
+ * transfer the object to the Running state.
+ *
+ * \note Even though the state of an object (visible to the rest of
+ * the world through Drainable::getState()) could be used to determine
+ * if all objects have entered the Drained state, the protocol is
+ * actually a bit more elaborate. See Drainable::drain() for details.
+ */
+enum class DrainState {
+    Running,  /** Running normally */
+    Draining, /** Draining buffers pending serialization/handover */
+    Drained   /** Buffers drained, ready for serialization/handover */
+};
+#endif
 
 /**
  * This class coordinates draining of a System.
@@ -141,30 +167,6 @@ class DrainManager
 class Drainable
 {
   public:
-    /**
-     * Object drain/handover states
-     *
-     * An object starts out in the Running state. When the simulator
-     * prepares to take a snapshot or prepares a CPU for handover, it
-     * calls the drain() method to transfer the object into the
-     * Draining or Drained state. If any object enters the Draining
-     * state (drain() returning >0), simulation continues until it all
-     * objects have entered the Drained state.
-     *
-     * Before resuming simulation, the simulator calls resume() to
-     * transfer the object to the Running state.
-     *
-     * \note Even though the state of an object (visible to the rest
-     * of the world through getState()) could be used to determine if
-     * all objects have entered the Drained state, the protocol is
-     * actually a bit more elaborate. See drain() for details.
-     */
-    enum State {
-        Running,  /** Running normally */
-        Draining, /** Draining buffers pending serialization/handover */
-        Drained   /** Buffers drained, ready for serialization/handover */
-    };
-
     Drainable();
     virtual ~Drainable();
 
@@ -225,15 +227,13 @@ class Drainable
      */
     virtual void memInvalidate() {};
 
-    State getDrainState() const { return _drainState; }
+    DrainState getDrainState() const { return _drainState; }
 
   protected:
-    void setDrainState(State new_state) { _drainState = new_state; }
-
+    void setDrainState(DrainState new_state) { _drainState = new_state; }
 
   private:
-    State _drainState;
-
+    DrainState _drainState;
 };
 
 DrainManager *createDrainManager();

diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc
index 2c4ba48f6eda1208aa41a748337d07b92e7cd1a5..9ea51eb9300eb348d796e7b6d18834d226640306 100644 (file)
--- a/src/sim/sim_object.cc
+++ b/src/sim/sim_object.cc
@@ -183,7 +183,7 @@ debugObjectBreak(const char *objs)
 unsigned int
 SimObject::drain(DrainManager *drain_manager)
 {
-    setDrainState(Drained);
+    setDrainState(DrainState::Drained);
     return 0;
 }
 

diff --git a/src/sim/system.cc b/src/sim/system.cc
index f781377f7e397746edb78b181f634de603336bde..3d473761724ed3cc71995ef0d934dfa82b0a174d 100644 (file)
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -191,7 +191,7 @@ System::getMasterPort(const std::string &if_name, PortID idx)
 void
 System::setMemoryMode(Enums::MemoryMode mode)
 {
-    assert(getDrainState() == Drainable::Drained);
+    assert(getDrainState() == DrainState::Drained);
     memoryMode = mode;
 }
 
@@ -358,7 +358,7 @@ System::isMemAddr(Addr addr) const
 unsigned int
 System::drain(DrainManager *dm)
 {
-    setDrainState(Drainable::Drained);
+    setDrainState(DrainState::Drained);
     return 0;
 }