Fixed handling of boolean attributes (backends)

diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc
index f9c6d364f5d4958235d648cbb26fb1ee4168cc43..6fd3a43cdde7e39a28727dc6ee5a8c098adbc975 100644 (file)
--- a/backends/autotest/autotest.cc
+++ b/backends/autotest/autotest.cc
@@ -109,7 +109,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
                                fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());
                        } else if (wire->port_input) {
                                count_ports++;
-                               bool is_clksignal = wire->attributes.count("\\gentb_clock") > 0;
+                               bool is_clksignal = wire->get_bool_attribute("\\gentb_clock");
                                for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); it3++)
                                for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); it4++) {
                                        if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
@@ -120,11 +120,11 @@ static void autotest(FILE *f, RTLIL::Design *design)
                                                        is_clksignal = true;
                                        }
                                }
-                               if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
+                               if (is_clksignal && !wire->get_bool_attribute("\\gentb_constant")) {
                                        signal_clk[idy("sig", mod->name, wire->name)] = wire->width;
                                } else {
                                        signal_in[idy("sig", mod->name, wire->name)] = wire->width;
-                                       if (wire->attributes.count("\\gentb_constant") > 0)
+                                       if (wire->get_bool_attribute("\\gentb_constant"))
                                                signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string();
                                }
                                fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index f878806165ffa425ad1b1ab5e9e977125b412fce..747ba17d33236e9d5f84ab8fde92b18bfcb833f6 100644 (file)
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -298,7 +298,7 @@ struct BlifBackend : public Backend {
                for (auto module_it : design->modules)
                {
                        RTLIL::Module *module = module_it.second;
-                       if ((module->attributes.count("\\placeholder") > 0) > 0)
+                       if ((module->get_bool_attribute("\\placeholder")) > 0)
                                continue;
 
                        if (module->processes.size() != 0)

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 4e38029a9dfad95f12c1bec9e29da5cefbe742ac..f898dc6d757324c4bbfac5a97e63727bc002b18e 100644 (file)
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -118,7 +118,7 @@ struct EdifBackend : public Backend {
                for (auto module_it : design->modules)
                {
                        RTLIL::Module *module = module_it.second;
-                       if ((module->attributes.count("\\placeholder") > 0) > 0)
+                       if (module->get_bool_attribute("\\placeholder"))
                                continue;
 
                        if (top_module_name.empty())
@@ -132,7 +132,7 @@ struct EdifBackend : public Backend {
                        for (auto cell_it : module->cells)
                        {
                                RTLIL::Cell *cell = cell_it.second;
-                               if (!design->modules.count(cell->type) || design->modules.at(cell->type)->attributes.count("\\placeholder")) {
+                               if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\placeholder")) {
                                        lib_cell_ports[cell->type];
                                        for (auto p : cell->connections) {
                                                if (p.second.width > 1)
@@ -200,7 +200,7 @@ struct EdifBackend : public Backend {
                for (auto module_it : design->modules)
                {
                        RTLIL::Module *module = module_it.second;
-                       if ((module->attributes.count("\\placeholder") > 0) > 0)
+                       if (module->get_bool_attribute("\\placeholder"))
                                continue;
 
                        SigMap sigmap(module);

diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 513c175310d2979f5a691c2c0c3512e470c6e889..83db8908cf26cda3cc711c3564c6ac201147715f 100644 (file)
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -132,7 +132,7 @@ struct IntersynthBackend : public Backend {
                        RTLIL::Module *module = module_it.second;
                        SigMap sigmap(module);
 
-                       if (module->attributes.count("\\placeholder") > 0)
+                       if (module->get_bool_attribute("\\placeholder"))
                                continue;
                        if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
                                continue;

diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 6932e14207176bae164c221480d6e36486ff1f9e..e6e4ab4b045a6931e69dcccbc77f3f9f318b59cd 100644 (file)
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -181,7 +181,7 @@ struct SpiceBackend : public Backend {
                for (auto module_it : design->modules)
                {
                        RTLIL::Module *module = module_it.second;
-                       if ((module->attributes.count("\\placeholder") > 0) > 0)
+                       if (module->get_bool_attribute("\\placeholder"))
                                continue;
 
                        if (module->processes.size() != 0)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 0eee4af40f4d222e3f98684fea8718c770dc048a..88a48b58423b7e170ba7a6edc6a5f9dfc26fa32c 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -957,7 +957,7 @@ struct VerilogBackend : public Backend {
                extra_args(f, filename, args, argidx);
 
                for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
-                       if ((it->second->attributes.count("\\placeholder") > 0) != placeholders)
+                       if (it->second->get_bool_attribute("\\placeholder") != placeholders)
                                continue;
                        if (selected && !design->selected_whole_module(it->first)) {
                                if (design->selected_module(it->first))