(no commit message)

diff --git a/3d_gpu/architecture/inorder_model.mdwn b/3d_gpu/architecture/inorder_model.mdwn
index a848c4e4ed2456f6f94ef859bb2a9f26dead8999..112a823e38eef69e7097125a79e2b4f75aa75cf0 100644 (file)
--- a/3d_gpu/architecture/inorder_model.mdwn
+++ b/3d_gpu/architecture/inorder_model.mdwn
@@ -14,11 +14,11 @@ instruction will take tens of clock cycles to complete.  In-development
 (Andrey to research and link to the relevant bugreport) is an in-order
 core and following on from that will be an out-of-order core.
 
-A Single-Issue In-Order control unit will allow every pipepline to be active,
+A Single-Issue In-Order control unit (written 12+ months ago) will allow every pipepline to be active,
 and raises the ideal maximum throughput to 1 instruction per clock cycle,
 bearing any register hazards.
 
-This control unit has not been written in HDL yet (incorrect: the first version was written 18 months ago, and is in soc/ and there are options in the Makefile to enable it), however there's currently a
+This control unit has not been written in HDL yet (incorrect: the first version was written 12+ months ago, and is in soc/ and there are options in the Makefile to enable it), however there's currently a
 task to develop the model for the simulator first. The model will be used to
 determine performance.