};
#define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
-#define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
struct ac_nir_context {
struct ac_llvm_context ac;
LLVMBasicBlockRef continue_block;
LLVMBasicBlockRef break_block;
- LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
-
int num_locals;
LLVMValueRef *locals;
};
instr->variables[0]->var->type, false);
count -= chan / 4;
LLVMValueRef tmp_vec = ac_build_gather_values_extended(
- &ctx->ac, ctx->outputs + idx + chan, count,
+ &ctx->ac, ctx->abi->outputs + idx + chan, count,
stride, true, true);
values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
indir_index, "");
} else {
values[chan] = LLVMBuildLoad(ctx->ac.builder,
- ctx->outputs[idx + chan + const_index * stride],
+ ctx->abi->outputs[idx + chan + const_index * stride],
"");
}
}
instr->variables[0]->var->type, false);
count -= chan / 4;
LLVMValueRef tmp_vec = ac_build_gather_values_extended(
- &ctx->ac, ctx->outputs + idx + chan, count,
+ &ctx->ac, ctx->abi->outputs + idx + chan, count,
stride, true, true);
tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
value, indir_index, "");
- build_store_values_extended(&ctx->ac, ctx->outputs + idx + chan,
+ build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
count, stride, tmp_vec);
} else {
- temp_ptr = ctx->outputs[idx + chan + const_index * stride];
+ temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
}
/* loop num outputs */
idx = 0;
- for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
+ for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
LLVMValueRef *out_ptr = &addrs[i * 4];
int length = 4;
int slot = idx;
result = visit_interp(ctx, instr);
break;
case nir_intrinsic_emit_vertex:
- ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->outputs);
+ ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
break;
case nir_intrinsic_end_primitive:
ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
for (unsigned i = 0; i < attrib_count; ++i) {
for (unsigned chan = 0; chan < 4; chan++) {
- ctx->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
+ ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
}
}
radv_load_output(struct nir_to_llvm_context *ctx, unsigned index, unsigned chan)
{
LLVMValueRef output =
- ctx->nir->outputs[radeon_llvm_reg_index_soa(index, chan)];
+ ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
return LLVMBuildLoad(ctx->ac.builder, output, "");
}
int i;
if (ctx->options->key.has_multiview_view_index) {
- LLVMValueRef* tmp_out = &ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
+ LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
if(!*tmp_out) {
for(unsigned i = 0; i < 4; ++i)
- ctx->nir->outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
+ ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
}
ac_build_export(&ctx->ac, &pos_args[i]);
}
- for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
+ for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
LLVMValueRef values[4];
if (!(ctx->output_mask & (1ull << i)))
continue;
uint64_t max_output_written = 0;
LLVMValueRef lds_base = NULL;
- for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
+ for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
int param_index;
int length = 4;
LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
}
- for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
+ for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
LLVMValueRef dw_addr = NULL;
- LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
+ LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
int param_index;
int length = 4;
LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
vertex_dw_stride, "");
- for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
- LLVMValueRef *out_ptr = &ctx->nir->outputs[i * 4];
+ for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
+ LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
int length = 4;
if (!(ctx->output_mask & (1ull << i)))
LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
struct ac_export_args color_args[8];
- for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
+ for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
LLVMValueRef values[4];
bool last = false;
phi_post_pass(&ctx);
if (nir->info.stage != MESA_SHADER_COMPUTE)
- ctx.abi->emit_outputs(ctx.abi, RADEON_LLVM_MAX_OUTPUTS,
- ctx.outputs);
+ ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
+ ctx.abi->outputs);
free(ctx.locals);
ralloc_free(ctx.defs);
LLVMConstInt(ctx->ac.i32, 4, false), "");
int idx = 0;
- for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
+ for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
int length = 4;
int slot = idx;
int slot_inc = 1;
0, 1, 1, true, false);
LLVMBuildStore(ctx->ac.builder,
- ac_to_float(&ctx->ac, value), ctx->nir->outputs[radeon_llvm_reg_index_soa(i, j)]);
+ ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
}
idx += slot_inc;
}