x86: implement x87 fp instruction fnstsw

This patch implements the fnstsw instruction. The code was originally written
by Vince Weaver. Gabe had made some comments about the code, but those were
never addressed. This patch addresses those comments.

diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 0b5523864593b388663ebf12fcc2a581dd821de4..5305b1058f8c150ac84ca863f451ae8eec44add6 100644 (file)
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -127,6 +127,13 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
     if (miscReg == MISCREG_TSC) {
         return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
     }
+
+    if (miscReg == MISCREG_FSW) {
+        MiscReg fsw = regVal[MISCREG_FSW];
+        MiscReg top = regVal[MISCREG_X87_TOP];
+        return (fsw & (~(7ULL << 11))) + (top << 11);
+    }
+
     return readMiscRegNoEffect(miscReg);
 }
 

diff --git a/src/arch/x86/isa/decoder/x87.isa b/src/arch/x86/isa/decoder/x87.isa
index 4ed902192ea539168c1995c3021255ffb533eab1..3af68cd5406113396d5cabd7022a7a768359cbf6 100644 (file)
--- a/src/arch/x86/isa/decoder/x87.isa
+++ b/src/arch/x86/isa/decoder/x87.isa
@@ -112,7 +112,7 @@ format WarnUnimpl {
                     0x6: fsin();
                     0x7: fcos();
                 }
-                default: fnstcw_Mw();
+                default: Inst::FNSTCW(Mw);
             }
         }
         //0x2: esc2();
@@ -247,7 +247,7 @@ format WarnUnimpl {
             }
             0x7: decode MODRM_MOD {
                 0x3: Inst::UD2();
-                default: fnstsw();
+                default: Inst::FNSTSW(Mw);
             }
         }
         //0x6: esc6();
@@ -310,7 +310,7 @@ format WarnUnimpl {
             }
             0x4: decode MODRM_MOD {
                 0x3: decode MODRM_RM {
-                    0x0: fnstsw();
+                    0x0: Inst::FNSTSW(rAw);
                     default: Inst::UD2();
                 }
                 default: fbld();

diff --git a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py
index 0fc4ef7b79024bc5310f206774ff8e0d2ac51741..5657c8d47b6c8d91da0e19d4bdcfa288d97a5c7f 100644 (file)
--- a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py
+++ b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py
@@ -38,5 +38,15 @@
 microcode = '''
 # FLDCW
 # FSTCW
-# FNSTCW
+
+def macroop FNSTCW_M {
+    rdval t1, fcw
+    st t1, seg, sib, disp, dataSize=2
+};
+
+def macroop FNSTCW_P {
+    rdip t7
+    rdval t1, fcw
+    st t1, seg, sib, disp, dataSize=2
+};
 '''

diff --git a/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py b/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py
index 2739852a4693ce16b71353b8947b5afc510c1546..65ff8006b4f6f7c54e24baebbe912e226925dca8 100644 (file)
--- a/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py
+++ b/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py
@@ -36,6 +36,22 @@
 # Authors: Gabe Black
 
 microcode = '''
+
 # FSTSW
-# FNSTSW
+
+def macroop FNSTSW_R {
+    rdval t1, fsw
+    mov rax, rax, t1, dataSize=2
+};
+
+def macroop FNSTSW_M {
+    rdval t1, fsw
+    st t1, seg, sib, disp, dataSize=2
+};
+
+def macroop FNSTSW_P {
+    rdip t7
+    rdval t1, fsw
+    st t1, seg, riprel, disp, dataSize=2
+};
 '''

diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 10404ec7acb311ad3a55b969a187aff5300f6ad5..b1fdfb54c46cf5d291d5181ee4e3f138a50b50c2 100644 (file)
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -207,6 +207,12 @@ let {{
     assembler.symbols["sti"] = stack_index("env.reg")
     assembler.symbols["stim"] = stack_index("env.regm")
 
+    def readFpReg(reg_name):
+        return regIdx("MISCREG_%s" % reg_name)
+
+    assembler.symbols["fsw"] = readFpReg("FSW")
+    assembler.symbols["fcw"] = readFpReg("FCW")
+
     macroopDict = assembler.assemble(microcode)
 
     decoder_output += mainRom.getDefinition()