Simulation model verilog fix

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 2458c1ca0f4c1924507c4bdc33de0b101dde41b1..07fadfa10c3a76b6319038ebc19948912f1a2b48 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -281,19 +281,6 @@ endmodule
 
 // ---------------------------------------
 
-module OB(input I, output O);
-assign O = I;
-endmodule
-
-// ---------------------------------------
-
-module BB(input I, T, output O, inout B);
-assign B = T ? 1'bz : I;
-assign O = B;
-endmodule
-
-// ---------------------------------------
-
 module INV(input A, output Z);
        assign Z = !A;
 endmodule

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 50d588a9e04ea00ed76aa5cb9ca7c47ebbfed2c6..f4598dcf4cc483dd77f794890858dd531e6711c5 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -282,7 +282,7 @@ module RAM32X1D (
   output DPO, SPO,
   input  D, WCLK, WE,
   input  A0, A1, A2, A3, A4,
-  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
   parameter INIT = 32'h0;
   parameter IS_WCLK_INVERTED = 1'b0;