No point logging constant bit

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 0e8ea65bff0eafb3ba5f070889f96e6e5175c61d..b7a5d5761e45546e3a47771df57af5ee3f6dce17 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -110,7 +110,7 @@ struct XAigerWriter
                }
 
                if (bit == State::Sx || bit == State::Sz) {
-                       log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit));
+                       log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
                        a = aig_map.at(State::S0);
                }