radv/gfx10: fix VS input VGPRs with the legacy path
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 23 Jul 2019 09:52:36 +0000 (11:52 +0200)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Wed, 24 Jul 2019 06:23:21 +0000 (08:23 +0200)
For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/vulkan/radv_nir_to_llvm.c
src/amd/vulkan/radv_shader.c

index 336bae28614c542097fe5abdb3adbda4c5dc741c..cf73cdc692bc1d527673c35b409845d1f672f47d 100644 (file)
@@ -852,9 +852,15 @@ declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
                        }
                } else {
                        if (ctx->ac.chip_class >= GFX10) {
-                               add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
-                               add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
-                               add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
+                               if (ctx->options->key.vs_common_out.as_ngg) {
+                                       add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
+                                       add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
+                                       add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
+                               } else {
+                                       add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
+                                       add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
+                                       add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
+                               }
                        } else {
                                add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
                                add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
index 736388c555cb871f30b099cd990404375c6a2cd4..5fd1022b05a2d243f1562ca17d757b605807fed8 100644 (file)
@@ -765,7 +765,7 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice,
                        if (info->vs.export_prim_id) {
                                vgpr_comp_cnt = 2;
                        } else if (info->info.vs.needs_instance_id) {
-                               vgpr_comp_cnt = 1;
+                               vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
                        } else {
                                vgpr_comp_cnt = 0;
                        }
@@ -837,7 +837,11 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice,
 
                if (es_type == MESA_SHADER_VERTEX) {
                        /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
-                       es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0;
+                       if (info->info.vs.needs_instance_id) {
+                               es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
+                       } else {
+                               es_vgpr_comp_cnt = 0;
+                       }
                } else if (es_type == MESA_SHADER_TESS_EVAL) {
                        es_vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
                } else {