Revert "Be mindful that sigmap(wire) could have dupes when checking \init"

This reverts commit f46ac1df9f8847dac9d9851f2f948d93a1064ff1.

diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 93a4f225ef8d984a90f8e9019e7d2c042c1cc599..430bba1e82cec5139afaacb4182723b99f8edb28 100644 (file)
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -265,18 +265,15 @@ struct SatHelper
                                RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
                                log_assert(lhs.size() == rhs.size());
 
-                               dict<RTLIL::SigBit,SigBit> seen_init;
                                RTLIL::SigSpec removed_bits;
                                for (int i = 0; i < lhs.size(); i++) {
                                        RTLIL::SigSpec bit = lhs.extract(i, 1);
-                                       if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit) || seen_init.at(bit, rhs[i]) != rhs[i]) {
+                                       if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) {
                                                removed_bits.append(bit);
                                                lhs.remove(i, 1);
                                                rhs.remove(i, 1);
                                                i--;
                                        }
-                                       else
-                                               seen_init[bit] = rhs[i];
                                }
 
                                if (removed_bits.size())