only add pc_i in DMI mode

running MMU test

diff --git a/libresoc/core.py b/libresoc/core.py
index f22925bbd7c045f7483d65579956a9f5faa9db0c..ec1c02995374a9861eb002c52a8c3d2ef44502ff 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -241,8 +241,6 @@ class LibreSoC(CPU):
             i_rst              = ResetSignal() | self.reset,
 
             # Monitoring / Debugging
-            i_pc_i             = Signal(64),
-            i_pc_i_ok          = 0,
             i_core_bigendian_i = 0, # Signal(),
             o_busy_o           = Signal(),   # not connected
             o_memerr_o         = Signal(),   # not connected
@@ -271,6 +269,8 @@ class LibreSoC(CPU):
                 i_dmi_we_i            = self.dmi_wr,
                 o_dmi_ack_o           = self.dmi_ack,
             ))
+            self.cpu_params['i_pc_i'] = Signal(64)
+            self.cpu_params['i_pc_i_ok'] = 0
 
         # add clock select, pll output
         if "ls180" in variant and "pll" not in variant:

diff --git a/sim.py b/sim.py
index 550339e46a22169fe19510da5d3032202f3f8aec..accac4fabc3196f3f39c0c1f3caf396953f69a69 100755 (executable)
--- a/sim.py
+++ b/sim.py
@@ -64,7 +64,9 @@ class LibreSoCSim(SoCSDRAM):
         #            "tests/decrementer/decrementer.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
-        ram_fname = None
+        ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+                    "tests/mmu/mmu.bin"
+        #ram_fname = None
 
         # reserve XICS ICP and XICS memory addresses.
         self.mem_map['xicsicp'] = 0xc0004000